Fuse array structure
AssigneeNanya Technology Corporation
InventorShian-Jyh Lin
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a substrate including a substrate including a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region; a control gate structure disposed over the first doped region and electrically connected to a control bit line; a fuse gate structure disposed over the second doped region and electrically connected to a fuse bit line; and a buried word to line disposed between the control gate structure and the fuse gate structure, wherein the buried word line is disposed within the recess of the substrate.
Claims14
A semiconductor structure, comprising:
- a substrate including a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region;
- a control gate structure disposed over the first doped region and electrically connected to a control bit line;
- a fuse gate structure disposed over the second doped region and electrically connected to a fuse bit line, wherein the fuse gate structure includes a fuse dielectric disposed on and contacted with the second doped region;
- and
- a buried word line disposed between the control gate structure and the fuse gate structure, wherein the buried word line is disposed within the recess of the substrate.
Dependencies are inferred from the claim text.