Unified micro system with memory IC and logic IC

An unified IC system, comprising:

• a DRAM chip comprising:
• a plurality of DRAM cells, wherein each DRAM cell comprises a first transistor and a capacitor;
• and
• a DRAM bridge area comprising a plurality of DRAM input/output (I/O) pads and a plurality of third transistors;
• and
• a logic chip physically separated from the DRAM chip, comprising:
• a plurality of second transistors;
• and
• a logic bridge area, wherein the logic bridge area comprises a plurality of logic I/O pads, and the plurality of DRAM I/O pads are electrically coupled to the plurality of logic I/O pads;
• wherein the DRAM chip does not include a voltage translation circuit or an off-chip driver positioned before the plurality of DRAM input/output (I/O) pads;
• wherein the DRAM chip comprises a first memory region with a first portion of the plurality of DRAM cells and a second memory region with a second portion of the plurality of DRAM cells, wherein the first memory region includes a plurality of first micro pads for testing and the second memory region includes a plurality of second micro pads for testing.

An unified IC system, comprising:

• a DRAM chip comprising:
• a plurality of DRAM cells, wherein each DRAM cell comprises a first transistor and a capacitor;
• and
• a DRAM bridge area comprising a plurality of DRAM input/output (I/O) pads and a plurality of third transistors;
• and
• a logic chip physically separated from the DRAM chip, comprising:
• a plurality of second transistors;
• and
• a logic bridge area, wherein the logic bridge area comprises a plurality of logic I/O pads, and the plurality of DRAM I/O pads are electrically coupled to the plurality of logic I/O pads;
• wherein the DRAM chip does not include a voltage translation circuit or an off-chip driver positioned before the plurality of DRAM input/output (I/O) pads;
• wherein the DRAM chip comprises a first memory region with a first portion of the plurality of DRAM cells and a second memory region with a second portion of the plurality of DRAM cells, wherein the first memory region includes a plurality of first bidirectional repeaters and the second memory region includes a plurality of second bidirectional repeaters in the second memory region.

An unified IC system, comprising:

• a DRAM chip comprising:
• a plurality of DRAM cells, wherein each DRAM cell comprises a first transistor and a capacitor;
• and
• a DRAM bridge area comprising a plurality of DRAM input/output (I/O) pads and a plurality of third transistors;
• and
• a logic chip physically separated from the DRAM chip, comprising:
• a plurality of second transistors;
• and
• a logic bridge area, wherein the logic bridge area comprises a plurality of logic I/O pads, and the plurality of DRAM I/O pads are electrically coupled to the plurality of logic I/O pads;
• wherein the plurality of DRAM input/output (I/O) pads comprises a first signal pad related to a data path transmission and a second signal pad related to the data path transmission, and there is no multiplexing circuits positioned before the first signal pads and the second signal pads in the DRAM chip;
• wherein the first signal pads are a row address interface and the second signal pads are a column address interface physically independent from the row address interface.