US 11,456,291 B2 · Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods

Abstract

Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

Claims24

Dependent claims

An integrated circuit (IC) package, comprising:

a first metallization structure comprising at least one first interconnect layer;
a second metallization structure comprising at least one second interconnect layer;
and
an IC die module disposed between the first metallization structure and the second metallization structure, the IC die module comprising:
a first IC die comprising a first active surface and a first non-active surface;
a second IC die comprising a second active surface and a second non-active surface;
and
a compression bond between the first non-active surface of the first IC die and the second non-active surface of the second IC die coupling the first non-active surface of the first IC die to the second non-active surface of the second IC die;
the first active surface of the first IC die is electrically coupled to a first interconnect layer of the at least one first interconnect layer of the first metallization structure;
and
the second active surface of the second IC die is electrically coupled to a second interconnect layer of the at least one second interconnect layer of the second metallization structure.

8 more elements

A method of fabricating an integrated circuit (IC) package, comprising:

fabricating a first metallization structure comprising at least one first interconnect layer:
fabricating a second metallization structure comprising at least one second interconnect layer;
fabricating an IC die module disposed between the first metallization structure and the second metallization structure, comprising:
providing a first IC die comprising a first active surface and a first non-active surface;
providing a second IC die comprising a second active surface and a second non-active surface;
and
compression bonding the first non-active surface of the first IC die to the second non-active surface of the second IC die to couple the first IC die to the second IC die;
electrically coupling the first active surface of the first IC die to a first interconnect layer of the at least one first interconnect layer of the first metallization structure;
and
electrically coupling the second active surface of the second IC die to a second interconnect layer of the at least one second interconnect layer of the second metallization structure.

7 more elements

Dependencies are inferred from the claim text.

Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods

Life of this patent

Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods

Life of this patent

Abstract

Claims24