Three-dimensional memory device with backside source contact
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsKun Zhang, Linchun Wu, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
Life of this patent
Estimating the term…
Abstract
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.
Claims20
A three-dimensional (3D) memory device, comprising:
- a substrate;
- a peripheral circuit on the substrate;
- a memory stack comprising interleaved conductive layers and dielectric layers above the peripheral circuit;
- a first semiconductor layer above the memory stack;
- a second semiconductor layer above and in contact with the first semiconductor layer;
- a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer;
- and
- a source contact above the memory stack and in contact with the second semiconductor layer.
A three-dimensional (3D) memory device, comprising:
- a substrate;
- a memory stack comprising interleaved conductive layers and dielectric layers above the substrate;
- an N-type doped semiconductor layer above the memory stack;
- a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer;
- and
- a source contact above the memory stack and in contact with the N-type doped semiconductor layer.
A three-dimensional (3D) memory device, comprising:
- a first semiconductor structure comprising a peripheral circuit;
- a second semiconductor structure comprising:
- a memory stack comprising interleaved conductive layers and dielectric layers;
- an N-type doped semiconductor layer;
- a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuit;
- and
- an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks;
- and
- a bonding interface between the first semiconductor structure and the second semiconductor structure.
Dependencies are inferred from the claim text.