Chip package structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLing-Wei Li, Jung-Hua Chang, Cheng-Lin Huang
Life of this patent
Estimating the term…
Abstract
A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a chip over a first surface of the first substrate. The chip package structure includes a barrier layer over a second surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure. The chip package structure includes a conductive bump over the conductive pad.
Claims20
A chip package structure, comprising:
- a first substrate;
- a conductive via structure passing through the first substrate;
- a chip over a first surface of the first substrate;
- a barrier layer over a second surface of the first substrate, wherein the barrier layer is in direct contact with the first substrate;
- an insulating layer over the barrier layer;
- a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure;
- and
- a conductive bump over the conductive pad, wherein the conductive bump and the conductive via structure are spaced apart from each other from a top view of the conductive pad, the conductive bump, and the conductive via structure, the conductive bump is electrically connected to the conductive via structure through the conductive pad, and the conductive bump is in direct contact with the conductive pad.
A chip package structure, comprising:
- a first substrate;
- a conductive via structure passing through the first substrate;
- a chip over a first surface of the first substrate;
- a barrier layer over a second surface of the first substrate, wherein the barrier layer is in direct contact with the first substrate;
- an insulating layer over the barrier layer;
- a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure;
- and
- a conductive bump over the conductive pad, wherein the conductive bump and the conductive via structure are misaligned in a vertical direction perpendicular to the second surface, and the conductive pad is in direct contact with the conductive bump and the conductive via structure.
A chip package structure, comprising:
- a first substrate;
- a conductive via structure passing through the first substrate;
- a chip over a first surface of the first substrate;
- a barrier layer over a second surface of the first substrate, wherein the barrier layer is in direct contact with the first substrate;
- a first insulating layer over the barrier layer;
- a conductive pad over the first insulating layer and passing through the first insulating layer and the barrier layer to connect with the conductive via structure;
- and
- a conductive bump over the conductive pad;
- and
- a second insulating layer over the first insulating layer and the conductive pad, wherein a portion of the second insulating layer is embedded in the conductive pad over the conductive via structure, and the conductive pad is partially between the portion and the conductive via structure.
Dependencies are inferred from the claim text.