US 11,456,265 B2Granted

Semiconductor device and method of manufacturing the same

AssigneeRenesas Electronics Corporation

InventorTakashi Tonegawa

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Abstract

A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.

Claims19

Dependent claims

A method of manufacturing a semiconductor device, the method comprising:

(a) forming an interlayer insulating film over a main surface of a semiconductor substrate;
(b) forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film;
(c) forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns;
(d) forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film;
and
(e) forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer by plating over the portion of the second conductive film pattern exposed in the second opening portion,
wherein an area of the second opening portion is smaller than an area of the first opening portion,
wherein the semiconductor substrate is kept still without swinging when the first plated layer and the second plated layer are formed by plating, and
wherein a thickness of the second plated layer in a center of the second opening portion is greater than a thickness of the first plated layer in a center of the first opening portion.

6 more elements

A method of manufacturing a semiconductor device, the method comprising:

(a) forming an interlayer insulating film over a main surface of a semiconductor substrate;
(b) forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film;
(c) forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns;
(d) forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film;
and
(e) forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer by plating over the portion of the second conductive film pattern exposed in the second opening portion,
wherein an area of the second opening portion is smaller than an area of the first opening portion,
wherein a thickness of the second plated layer is greater than a thickness of the first plated layer,
wherein the semiconductor substrate is kept still without swinging when the first plated layer and the second plated layer are formed by plating,
wherein the first plated layer includes a first nickel plated layer,
wherein the second plated layer includes a second nickel plated layer,
wherein the (e) includes:
(e1) forming the first nickel plated layer over the portion of the first conductive film pattern exposed in the first opening portion, and the second nickel plated layer over the portion of the second conductive film pattern exposed in the second opening portion,
wherein a thickness of the second nickel plated layer is greater than a thickness of the first nickel plated layer, and
wherein, in the (e1), a film-forming speed of the second nickel plated layer is larger than a film-forming speed of the first nickel plated layer.

12 more elements

A method of manufacturing a semiconductor device, the method comprising:

(a) forming an interlayer insulating film over a main surface of a semiconductor substrate;
(b) forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film;
(c) forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns;
(d) forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film;
and
(e) forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer by plating over the portion of the second conductive film pattern exposed in the second opening portion,
wherein an area of the second opening portion is smaller than an area of the first opening portion,
wherein a thickness of the second plated layer is greater than a thickness of the first plated layer,
wherein the semiconductor substrate is kept still without swinging when the first plated layer and the second plated layer are formed by plating,
wherein the first plated layer includes a first nickel plated layer,
wherein the second plated layer includes a second nickel plated layer,
wherein the (e) includes:
(e1) forming the first nickel plated layer over the portion of the first conductive film pattern exposed in the first opening portion, and the second nickel plated layer over the portion of the second conductive film pattern exposed in the second opening portion,
wherein a thickness of the second nickel plated layer is greater than a thickness of the first nickel plated layer, and
wherein, in the (e1), the first nickel plated layer and the second nickel plated layer are grown in a state where a concentration of a reducing agent in a plating solution in a vicinity of the portion of the first conductive film pattern exposed in the first opening portion is lower than that in a vicinity of the portion of the second conductive film pattern exposed in the second opening portion.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/927,006Filed 13 Jul 2020 · continuation
Priority: JP JP2016-22218915 Nov 2016
Published: US 2020/0343207 A129 Oct 2020
Granted: 27 Sep 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification49 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 30/0295
Of vertical dmos [vdmos] fets: using recessing of the source electrodes
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 64/2527
For vertical or pseudo-vertical devices: for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies