US 11,456,257 B2Granted

Semiconductor package with dual sides of metal routing

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsShin-Puu Jeng, Shuo-Mao Chen, Hsien-Wen Liu, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin

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Abstract

A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

Claims20

Dependent claims

A semiconductor device comprising:

a die embedded in a first molding material, a first side of the die having a die connector;
a first conductive pillar embedded in the first molding material and laterally spaced apart from the die;
a redistribution structure at the first side of the die, the die connector being bonded to a conductive pad of the redistribution structure by solder, wherein the redistribution structure has an upper dielectric layer closest to the die, wherein an upper portion of the conductive pad extends above a first side of the upper dielectric layer facing the die, and a lower portion of the conductive pad extends into the upper dielectric layer and physically contacts an uppermost metal layer of the redistribution structure closest to the die, wherein sidewalls of the lower portion of the conductive pad physically contact the upper dielectric layer of the redistribution structure, wherein the solder is disposed on the upper portion of the conductive pad, wherein the first conductive pillar has an upper portion over the first side of the upper dielectric layer of the redistribution structure, and has a lower portion extending into the upper dielectric layer and physically contacting the uppermost metal layer of the redistribution structure, wherein the upper portion and the lower portion of the first conductive pillar have a same material composition;
a substrate at a second side of the die opposing the first side of the die, wherein the substrate comprises:
a dielectric core;
a via extending through the dielectric core;
a first conductive line along a first side of the dielectric core distal from the die;
a second conductive line along a second side of the dielectric core facing the die and electrically coupled to the via of the substrate;
a first dielectric layer along the first side of the dielectric core and covering the first conductive line;
and
a second dielectric layer along the second side of the dielectric core and covering the second conductive line;
and
a first solder region interposed between the first conductive pillar and the substrate, wherein the first solder region extends continuously from the first conductive pillar to the substrate, wherein the first solder region extends through the second dielectric layer and is in physical contact with the second conductive line, wherein first sidewalls of the first molding material contacting and extending along sidewalls of the first solder region are curved.

10 more elements

A semiconductor device comprising:

a redistribution structure;
a first die over the redistribution structure, wherein a die connector of the first die is bonded to a conductive pad of the redistribution structure by a first solder material, wherein the redistribution structure has an uppermost dielectric layer facing the first die, wherein the conductive pad has an upper portion extending above a first side of the uppermost dielectric layer facing the first die, and has a lower portion extending into the uppermost dielectric layer and physically contacting an uppermost metal layer of the redistribution structure closest to the first die, wherein sidewalls of the lower portion of the conductive pad physically contact the uppermost dielectric layer of the redistribution structure, wherein the first solder material is disposed on the upper portion of the conductive pad;
a conductive pillar over the redistribution structure and adjacent to the first die, the conductive pillar being electrically coupled to the redistribution structure, wherein the conductive pillar has an upper portion over the first side of the uppermost dielectric layer of the redistribution structure, and has a lower portion extending into the uppermost dielectric layer and physically contacting the uppermost metal layer of the redistribution structure, wherein the upper portion and the lower portion of the conductive pillar have a same material composition;
a first molding material over the redistribution structure, the first molding material being around the first die and around the conductive pillar;
a conductive joint over and bonded to the conductive pillar, wherein the conductive joint is a solder region, wherein first sidewalls of the first molding material contact and extend along second sidewalls of the conductive joint, wherein the first sidewalls of the first molding material are curved;
a first substrate over the first molding material and over the conductive joint, wherein the first substrate comprises a dielectric core, a first conductive line extending along a lower side of the dielectric core facing the first die, and a first solder resist layer along the lower side of the dielectric core covering the first conductive line, wherein the conductive joint extends into the first solder resist layer and physically contacts the first conductive line;
and
a semiconductor package bonded to a first side of the first substrate distal from the first molding material by a second solder material, wherein the semiconductor package comprises:
a second substrate;
a second die attached to a first side of the second substrate distal from the first substrate, wherein a second side of the second substrate facing the first substrate is spaced apart from the first substrate, wherein a conductive pad at the second side of the second substrate is bonded to an external connector of the first substrate by the second solder material;
and
a second molding material on the first side of the second substrate around the second die, wherein the second molding material and the second substrate have a same width such that sidewalls of the second molding material are vertically aligned with respective sidewalls of the second substrate.

9 more elements

A semiconductor device comprising:

a redistribution structure having a conductive pad at a first side of the redistribution structure;
a first substrate having conductive features, wherein the first substrate comprises a dielectric core, a first conductive line extending along a first side of the dielectric core facing the redistribution structure, and a first solder resist layer along the first side of the dielectric core covering the first conductive line;
a first die between the redistribution structure and the first substrate, wherein a die connector at a front side of the first die is attached to the conductive pad of the redistribution structure by a solder material, and a backside of the first die is spaced apart from the first substrate;
a conductive pillar attached to the first side of the redistribution structure, wherein the conductive pillar is spaced apart from the first die, wherein the redistribution structure has an upper dielectric layer closest to the first die, wherein an upper portion of the conductive pad extends above a first side of the upper dielectric layer facing the first die, and a lower portion of the conductive pad extends into the upper dielectric layer and physically contacts an uppermost metal layer of the redistribution structure closest to the first die, wherein sidewalls of the lower portion of the conductive pad physically contact the upper dielectric layer of the redistribution structure, wherein the solder material is disposed on the upper portion of the conductive pad, wherein the conductive pillar has an upper portion over the first side of the upper dielectric layer of the redistribution structure, and has a lower portion extending into the upper dielectric layer and physically contacting the uppermost metal layer of the redistribution structure, wherein the upper portion and the lower portion of the conductive pillar comprise a same conductive material;
a solder joint over a top surface of the conductive pillar distal from the redistribution structure, wherein the conductive pillar and the solder joint electrically couple the first substrate to the redistribution structure, wherein the solder joint extends into the first solder resist layer and is in physical contact with the first conductive line of the first substrate;
a first molding material between the first substrate and the redistribution structure, wherein the first molding material surrounds the first die, the conductive pillars, and the solder joint, wherein sidewalls of the first molding material contacting and extending along sidewalls of the solder joint are curved;
and
a semiconductor package bonded to a first side of the first substrate distal from the first molding material, wherein the semiconductor package comprises:
a second substrate bonded to the first side of the first substrate by solder;
a second die attached to a first side of the second substrate distal from the first substrate;
and
a second molding material on the first side of the second substrate around the second die.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/569,850Filed 13 Sep 2019 · division
Priority: 6 Jul 2017
Published: US 2020/0006234 A12 Jan 2020
Granted: 27 Sep 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification30 codes

H10W 70/611
Insulating or insulated package substrates; Interposers; Redistribution layers: for connecting multiple chips together
H10W 20/063
Of conductive parts of the interconnections: by forming conductive members before forming protective insulating material
H10W 70/614
For connecting multiple chips together: the multiple chips being integrally enclosed
H10W 70/635
Vias, e.g. via plugs: through-vias

Family

Application62/529,237Us provisional application · filed 6 Jul 2017
Application15/908,417Parent of this division · filed 28 Feb 2018
US 2020/0006234 A1Pre-grant publication · published 2 Jan 2020
US 10,867,924 B2Parent of this division
US 2019/0013273 A1Published application
US 11,456,257 B2This patent

From the US filing history. Foreign family members aren’t listed.