US 11,456,252 B2 · Semiconductor device having symmetric conductive interconnection patterns

Abstract

A method for fabricating a semiconductor device may include forming a stopper layer; forming an intermediate pattern material layer over the stopper layer; forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer; forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns; forming a conductive material layer to cover the second preliminary intermediate patterns; forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer; forming a filling layer between the preliminary conductive interconnection patterns; and forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.

Claims20

Dependent claims

A method for fabricating a semiconductor device, comprising:

forming a stopper layer;
forming an intermediate pattern material layer over the stopper layer;
forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer;
forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns;
forming a conductive material layer to cover the second preliminary intermediate patterns;
forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer;
forming a filling layer between the preliminary conductive interconnection patterns;
and
forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.

6 more elements

A method for fabricating a semiconductor device, comprising:

forming a lower interlayer dielectric layer over a substrate;
forming a stopper layer over the lower interlayer dielectric layer;
forming first preliminary intermediate patterns over the stopper layer;
forming second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns;
forming preliminary conductive interconnection patterns to cover top surfaces and both side surfaces of the second preliminary intermediate patterns;
forming a filling layer between the preliminary conductive interconnection patterns;
forming intermediate patterns with side surfaces, conductive interconnection patterns on the side surfaces of the intermediate patterns and filling patterns between the conductive interconnection patterns by removing a top portion of each of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns;
forming a capping layer over the intermediate patterns, the conductive interconnection patterns and the filling patterns;
and
forming an upper interlayer dielectric layer over the capping layer.

7 more elements

Dependencies are inferred from the claim text.

Semiconductor device having symmetric conductive interconnection patterns

Life of this patent

Semiconductor device having symmetric conductive interconnection patterns

Life of this patent

Abstract

Claims20