Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same

A fan-out silicon interposer comprising:

• a bridge die including an array of through-silicon via (TSV) structures, package-side metal pads contacting package-side end surfaces of the array of TSV structures, and a package-side dielectric material layer that laterally surrounds the package-side metal pads;
• an encapsulant interposer frame that laterally surrounds the bridge die;
• through-integrated-fan-out via (TIV) structures that vertically extends through the EMC interposer frame;
• a package-side redistribution structure located on the package-side metal pads and contacting the package-side dielectric material layer of the bridge die;
• and
• a die-side redistribution structure electrically connected to the array of TSV structures and including die-side bonding pads.

A method of forming a chip package structure, comprising:

• forming via structures through an upper portion of a silicon substrate;
• forming die-side metal interconnect structures over the via structures;
• forming an array of through-silicon via (TSV) structures by thinning a backside the silicon substrate, wherein the via structures vertically extend through an entire thickness of the thinned silicon substrate to become the array of TSV structures;
• forming package-side metal pads laterally surrounded by a package-side dielectric layer on backside surfaces of the array of TSV structures, whereby a bridge die is formed;
• disposing the bridge die over a carrier substrate;
• forming an encapsulant interposer frame around the bridge die and over the carrier substrate;
• forming a die-side redistribution structure over the bridge die and the encapsulant interposer frame;
• attaching at least one semiconductor die to the die-side redistribution structure;
• and
• forming a package-side redistribution structure comprising package-side redistribution dielectric layers over the package-side metal pads directly on the package-side dielectric material layer.