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US 11,456,241 B2Granted
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsSeokhyun Lee, Jongyoun Kim, Yeonho Jang, Jaegwon Jang
Life of this patent
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Abstract
A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.
Claims18
A semiconductor package comprising:
- a semiconductor chip;
- a redistribution structure below the semiconductor chip;
- a first insulating layer below the redistribution structure;
- a pad having an upper portion and a lower portion, the lower portion below the first insulating layer, the pad contacting the redistribution structure, the upper portion having a greater horizontal maximum length than the lower portion;
- a second insulating layer below the first insulating layer, wherein a lower surface of the second insulating layer and a lower surface of the lower portion of the pad are coplanar;
- and
- a bump contacting the lower surface of the lower portion of the pad.
4 more elements
A semiconductor package comprising:
- a bump;
- a pad on the bump, the pad having a lower portion and an upper portion, the upper portion having a greater horizontal maximum length than the lower portion;
- a first insulating layer spaced apart from the lower portion of the pad while in contact with a side surface and an upper surface of the upper portion of the pad;
- a first conductive pattern on the first insulating layer, the first conductive pattern including a first line portion and a first via portion protruding downward from the first line portion, the first via portion contacting the pad;
- a second insulating layer on the first insulating layer and the first conductive pattern;
- a second conductive pattern on the second insulating layer, the second conductive pattern including a second line portion and a second via portion protruding downward from the second line portion, the second via portion contacting the first line portion of the first conductive pattern;
- a semiconductor chip electrically connected to the second conductive pattern;
- and
- a third insulating layer below the first insulating layer,
- wherein a lower surface of the lower portion of pad is coplanar with a lower surface of the third insulating layer.
7 more elements
A semiconductor package comprising:
- a package substrate;
- a first bump below the package substrate;
- a second bump on the package substrate;
- an interposer on the second bump, the interposer including a pad on the second bump;
- a first semiconductor chip on the interposer;
- a first insulating layer on the pad;
- and
- a redistribution structure on the first insulating layer, the redistribution structure connecting the pad and the first semiconductor chip,
- an upper portion of the pad in a first opening in the first insulating layer, and
- the upper portion of the pad having a greater horizontal maximum length than a lower portion of the pad,
- wherein the interposer further comprises a second insulating layer below the first insulating layer, and a lower surface of the lower portion of the pad is coplanar with a lower surface of the second insulating layer.
8 more elements
Dependencies are inferred from the claim text.