Semiconductor device including a semiconductor chip connected with a plurality of main terminals

A semiconductor device configuring one arm of an upper-lower arm circuit, the semiconductor device comprising:

• a plurality of semiconductor elements that includes at least a first semiconductor element and a second semiconductor element;
• a plurality of main terminals;
• at least one signal terminal;
• and
• a connection portion,
• wherein:
• each of the plurality of semiconductor elements includes a first main electrode and second main electrode;
• a main current flows between the first main electrode and the second main electrode and through each of the plurality of main terminals;
• the plurality of main terminals includes two or more first main terminals connected to the first main electrode and two or more second main terminals connected to the second main electrode;
• each of the at least one signal terminal is (1) connected, by a binding wire, to a pad on the plurality of semiconductor elements and (2) electrically separated from the plurality of main terminals;
• the two or more first main terminals and the two or more second main terminals alternate adjacent to each other;
• a lateral surface of the each of the two or more first main terminals faces a lateral surface of an adjacent second main terminal of the two or more the second main terminals in one direction orthogonal to a thickness direction of the semiconductor element;
• the first semiconductor element and the second semiconductor element are spaced in the one direction and are connected in parallel between the two or more first main terminals and the two or more second main terminals;
• a main terminal group includes a subset of the plurality of main terminals that are continuously arranged in the one direction;
• the main terminal group includes four or more of the plurality of main terminals in a first group and a second group;
• at least a part of each of the plurality of main terminals in the first group is in a first region defined, in the one direction, by end surfaces of the first semiconductor element;
• at least a part of each of the plurality of main terminals in the second group is in a second region defined, in the one direction, by end surfaces of the second semiconductor element;
• the connection portion is a part of a lead frame with at least one of the two or more first main terminals or the two or more second main terminals;
• and
• a set of the plurality of main terminals from the two or more first main terminals or the two or more second main terminals are connected to each other by the connection portion.