Vertical semiconductor devices including vertical memory cells and peripheral circuits under the vertical memory cells

A vertical semiconductor device, comprising:

• a plurality of vertical memory cells on an upper surface of a first substrate;
• a first insulating interlayer covering the vertical memory cells on the first substrate;
• an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate;
• a second substrate having peripheral circuits thereon;
• a lower insulating interlayer covering the peripheral circuits on the second substrate, an upper surface of the lower insulating interlayer in contact with a lower surface of the adhesive layer;
• a plurality of through via contacts passing through at least the first insulating interlayer, each of the through via contacts in contact with a lower wiring of a corresponding one of the peripheral circuits;
• and
• a lower conductive layer between the first substrate and the adhesive layer, the lower conductive layer vertically and completely separating the first substrate from the adhesive layer,
• wherein the lower surface of the adhesive layer and the upper surface of the lower insulating interlayer serve as a bonding interface, and
• wherein voids are irregularly provided at the bonding interface.

A vertical semiconductor device, comprising:

• a plurality of vertical memory cells on an upper surface of a first substrate;
• an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate;
• peripheral circuits on a second substrate;
• a lower insulating interlayer covering the peripheral circuits on the second substrate, an upper surface of the lower insulating interlayer in contact with a lower surface of the adhesive layer;
• and
• a lower conductive layer between the first substrate and the adhesive layer, the lower conductive layer vertically and completely separating the first substrate from the adhesive layer,
• wherein the lower surface of the adhesive layer and the upper surface of the lower insulating interlayer serve as a bonding interface,
• wherein voids are irregularly provided at the bonding interface, and
• wherein the first substrate overlaps an upper surface of the second substrate, and the adhesive layer and the lower insulating interlayer are between the first and second substrates.