Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

A method of forming a self-aligned via on a semiconductor workpiece, the method comprising:

• receiving the workpiece comprising a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface;
• selectively depositing metal caps on the exposed surfaces of the metal features relative to the exposed dielectric material, the selectivity between the metal cap and the dielectric material being based, at least in part, on a higher metal cap layer deposition rate on the metal features than on the dielectric material;
• selectively forming a barrier layer on the metal caps relative to the exposed dielectric material;
• the selectivity between the metal cap and the dielectric material being based, at least in part, on a higher barrier layer deposition rate on the metal caps than on the dielectric material;
• selectively depositing a first dielectric material on the exposed surfaces of the dielectric layer to form a recess pattern in the first dielectric material, the selective deposition being based, at least in part, on a deposition rate of the first dielectric material being higher on the exposed surfaces than on the metal caps, the recess pattern comprising a sidewall including a portion of the first dielectric material;
• treating the workpiece to expose the metal caps at bottom surfaces of the recess pattern;
• and
• depositing an etch stop layer over the recess pattern.