Integrated circuit and method for manufacturing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuan-Wei Huang, Yi-Nien Su, Yu-Yu Chen, Jyu-Horng Shieh
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Abstract
An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.
Claims20
An integrated circuit structure, comprising:
- a plurality of conductive features within a dielectric layer overlying a substrate;
- a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer;
- a protection layer between sidewalls of the barrier layer and the dielectric layer;
- and
- a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features,
- wherein an upper surface of the dielectric layer is substantially flushed with upper surfaces of the conductive features.
A method for fabricating an integrated circuit structure, comprising:
- forming a plurality of first openings in a dummy layer over a substrate;
- forming a protection layer along sidewalls of the plurality of the first openings;
- forming a barrier layer over the plurality of the first openings;
- forming a plurality of conductive features in the plurality of the first openings, respectively, after the forming of the barrier layer;
- removing the dummy layer to form a plurality of second openings;
- and
- forming a dielectric layer having a void between two adjacent conductive features of the plurality of conductive features.
A method for fabricating an integrated circuit structure, comprising:
- forming a plurality of first openings in a dummy layer over a substrate;
- forming a plurality of conductive features in the plurality of first openings;
- removing at least a portion of the dummy layer to form a plurality of second openings;
- forming an upper dielectric layer covering the plurality of conductive features and filling in the plurality of the second openings with an air gap between two adjacent conductive features of the plurality of conductive features;
- and
- removing a top portion of the plurality of the conductive features and a top portion of the upper dielectric layer for planarization.
Dependencies are inferred from the claim text.