Integrated circuit structure and fabrication thereof

An integrated circuit (IC) structure comprising:

• a gate structure;
• gate spacers on either side of the gate structure;
• source/drain epitaxial structures adjacent to the gate spacers, respectively;
• a front-side interconnection structure on a front-side of the source/drain epitaxial structures;
• a backside dielectric layer on a backside of the source/drain epitaxial structures;
• and
• a backside via extending through the backside dielectric layer to the backside of a first one of the source/drain epitaxial structures, wherein the gate spacers have a concentration of a dopant decreasing toward the backside via.

A method comprising:

• forming a dummy gate structure over a substrate, and gate spacers on opposite sides of the dummy gate structure;
• epitaxially growing source/drain structures on regions of the substrate beyond the dummy gate structure and the gate spacers;
• forming an interlayer dielectric (ILD) layer over the source/drain structures;
• replacing the dummy gate structure with a metal gate structure;
• recessing the metal gate structure to fall below top ends of the gate spacers;
• forming a gate hard mask over the recessed metal gate structure;
• performing an ion implantation process to dope the gate hard mask;
• after performing the ion implantation process to dope the gate hard mask, etching the ILD layer to form source/drain contact openings over the source/drain structures, respectively;
• and
• forming source/drain contacts in the source/drain contact openings, respectively.