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US 11,456,100 B2Granted
MRAM stacks, MRAM devices and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShy-Jay Lin, Wilman Tsai, Ming-Yuan Song
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Abstract
Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
Claims20
A memory stack, comprising:
- a spin-orbit torque layer;
- a magnetic bias layer being in direct contact with the spin-orbit torque layer and having a first magnetic anisotropy;
- and
- a free layer disposed adjacent to the spin-orbit torque layer and having a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
1 more element
A memory stack, comprising:
- a spin-orbit torque layer;
- a synthetic free layer disposed over the spin-orbit torque layer and comprising:
- a first free layer with a perpendicular magnetic anisotropy;
- and
- a second free layer with a horizontal magnetic anisotropy;
- a tunneling barrier layer disposed over the synthetic free layer;
- and
- a reference layer disposed over the tunneling barrier layer.
5 more elements
A memory device, comprising:
- a substrate;
- a first transistor disposed over the substrate and having a first source/drain region;
- a second transistor disposed over the substrate and having a second source/drain region;
- and
- a MRAM cell disposed over the substrate and comprising:
- first and second bottom electrodes respectively coupled to the first source/drain region and the second source/drain region;
- a spin-orbit torque layer disposed over the first and second bottom electrodes;
- a synthetic free layer disposed over the spin-orbit torque layer and comprising two layers configured to have magnetic anisotropies perpendicular to each other;
- a tunneling barrier layer disposed over the synthetic free layer;
- a reference layer disposed over the tunneling barrier layer;
- and
- a top electrode disposed over the reference layer and coupled to a bit line.
9 more elements
Dependencies are inferred from the claim text.