Relinking scheme in sub-block mode
AssigneeWestern Digital Technologies, Inc.
InventorsChandramani, Sagar Shirpimutt
Life of this patent
Estimating the term…
Abstract
Aspects of a storage device including a memory and a controller are provided which allow sub-blocks with different sub-block addresses to be linked across multiple planes to form metablocks. The memory includes multiple blocks in different planes, where each of the blocks includes multiple sub-blocks. The controller links a first sub-block in a first plane and a second sub-block in a second plane with different sub-block addresses to form the metablock. After forming the metablock, the controller programs different word lines in the first and second sub-blocks when writing data to the metablock. Thus, the controller may write data to linked or relinked metablocks with different sub-block addresses, thereby improving die yield and memory capacity of the storage device.
Claims19
A storage device, comprising:
- a memory including a plurality of blocks in different planes, wherein each of the blocks includes a plurality of sub-blocks;
- and
- a controller configured to link a first one of the sub-blocks in a first one of the planes with a second one of the sub-blocks in a second one of the planes to form a metablock, wherein the first one of the sub-blocks and the second one of the sub-blocks are associated with different sub-block addresses;
- wherein the metablock is a logical grouping of the first one of the sub-blocks and the second one of the sub-blocks;
- wherein the controller is further configured, during a write operation associated with the metablock, to program a first word line in the first one of the sub-blocks and to subsequently program a second word line in the second one of the sub-blocks following a program failure responsive to programming of the first word line.
A storage device, comprising:
- a memory including a plurality of blocks in different planes, wherein each of the blocks includes a plurality of sub-blocks;
- and
- a controller configured to program a word line in a first one of the sub-blocks in one of the planes and to program a different word line in a second one of the sub-blocks in another one of the planes following a program failure responsive to programming of the word line, wherein the first one of the sub-blocks and the second one of the sub-blocks are parts of a metablock and include different sub-block addresses;
- wherein the metablock is a logical group including the first one of the sub-blocks and the second one of the sub-blocks.
A storage device, comprising:
- a memory including a plurality of blocks in different planes, wherein each of the blocks includes a plurality of sub-blocks;
- and
- a controller configured to link a first one of the sub-blocks in one of the planes with a second one of the sub-blocks in another one of the planes to form a metablock, wherein the first one of the sub-blocks and the second one of the sub-blocks are associated with different sub-block addresses;
- wherein the controller is further configured to program different word lines in the first one of the sub-blocks and the second one of the sub-blocks during a write operation associated with the metablock;
- wherein the metablock includes a logical address associated with the first one of the sub-blocks and the second one of the sub-blocks;
- wherein the different word lines include a first word line in the first one of the sub-blocks and a second word line in the second one of the sub-blocks, the controller being further configured to program the second word line following a program failure associated with the first word line.
Dependencies are inferred from the claim text.