Memory device testing, and associated methods, devices, and systems
AssigneeMicron Technology, Inc.
InventorsJason M. Johnson, Dennis G. Montierth
Life of this patent
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Abstract
Methods of testing memory devices are disclosed. A method may include reading from a number of memory addresses of a memory array of the memory device and identifying each memory address of the number of addresses as either a pass or a fail. The method may further include storing, for each identified fail, data associated with the identified fail in a buffer of the memory device. Further, the method may include conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester. Devices and systems are also disclosed.
Claims20
A method of testing a memory device, comprising:
- reading from a number of memory addresses of a memory array of the memory device;
- identifying each memory address of the number of memory addresses as either a pass or a fail;
- storing, for each identified fail, data associated with the identified fail in a buffer of the memory device;
- and
- conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester.
A device, comprising:
- a memory array;
- a buffer coupled to the memory array;
- and
- circuitry coupled to the memory array and the buffer and configured to:
- read data from a number of memory addresses of the memory array;
- compare the read data to known test data;
- responsive to the comparison, identify each memory address of the number of memory addresses as either a pass or a fail;
- store, for each identified fail, data associated with the identified fail in the buffer;
- and
- convey, to an external tester, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the external tester.
A system, comprising:
- a testing device;
- and
- at least one memory device operably coupled to the testing device and comprising:
- a memory array comprising a number of memory addresses;
- a first-in, first-out (FIFO) cache;
- and
- at least one circuit configured to:
- identify, responsive to at least one test operation, each memory address of the number of memory addresses as either a pass or a fail;
- store, for each identified fail, a number of fail data bits associated with the identified fail in the FIFO cache;
- and
- convey, to the testing device, at least some of the number of fail data bits associated with each identified fail without conveying address data associated with each identified pass to the testing device.
Dependencies are inferred from the claim text.