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US 11,456,047 B2Granted
Flash memory device with programmable logic circuit
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsHuangpeng Zhang, Shiyang Yang, Yu Wang, Huamin Cao, Ting Li, Xu Hou
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Abstract
Aspects of the disclosure provide a semiconductor memory device. The semiconductor memory device includes a memory cell array and peripheral circuitry coupled with the memory cell array. The memory cell array includes a plurality of memory cells. The peripheral circuitry includes programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions.
Claims19
A semiconductor memory device, comprising:
- a memory cell array comprising a plurality of memory cells;
- and
- peripheral circuitry coupled with the memory cell array, the peripheral circuitry comprising:
- programmable logic circuit that is configured, after the semiconductor memory device is powered on, to perform logic functions, wherein
- the memory cell array is formed on a first substrate of a first die, the peripheral circuitry is formed on a second substrate of a second die, and the memory cell array and the peripheral circuitry are bonded face to face and stacked in a direction perpendicular to the first substrate and the second substrate, and
- the configuration information for configuring the programmable logic circuit is read from the memory cell array on the first substrate of the first die to the peripheral circuitry on the second substrate of the second die through a first bonding structure connected to the memory cell array and a second bonding structure connected to the peripheral circuitry.
3 more elements
A method for forming a semiconductor memory device, comprising:
- determining logic functions for programmable logic circuit that is disposed in peripheral circuitry for a memory cell array in the semiconductor memory device, the memory cell array comprising non-volatile memory cells;
- determining configuration information for configuring the programmable logic circuit to perform the logic functions;
- and
- storing the configuration information in the non-volatile memory cells, the configuration information being used to configure the programmable logic circuit when the semiconductor memory device is powered on, wherein
- the memory cell array is formed on a first substrate of a first die, the peripheral circuitry is formed on a second substrate of a second die, and the memory cell array and the peripheral circuitry are bonded face to face and stacked in a direction perpendicular to the first substrate and the second substrate, and
- the configuration information for configuring the programmable logic circuit is read from the memory cell array on the first substrate of the first die to the peripheral circuitry on the second substrate of the second die through a first bonding structure connected to the memory cell array and a second bonding structure connected to the peripheral circuitry.
3 more elements
A method for using a semiconductor memory device, comprising:
- receiving configuration information for configuring programmable logic circuit that is disposed in peripheral circuitry for a memory cell array in the semiconductor memory device, the memory cell array comprising non-volatile memory cells;
- and
- storing the configuration information in the non-volatile memory cells, the configuration information being used to configure the programmable logic circuit when the semiconductor memory device is powered on, wherein
- the memory cell array is formed on a first substrate of a first die, the peripheral circuitry is formed on a second substrate of a second die, and the memory cell array and the peripheral circuitry are bonded face to face and stacked in a direction perpendicular to the first substrate and the second substrate, and
- the configuration information for configuring the programmable logic circuit is read from the memory cell array on the first substrate of the first die to the peripheral circuitry on the second substrate of the second die through a first bonding structure connected to the memory cell array and a second bonding structure connected to the peripheral circuitry.
2 more elements
Dependencies are inferred from the claim text.