Back to results
US 11,456,046 B2Granted
Memory device and clock locking method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorHundae Choi
Life of this patent
Estimating the term…
Abstract
A clock locking method of a memory device, may include performing an initial locking operation in a delay locked loop circuit before an internal voltage is stabilized, monitoring clock skew between a reference clock and a feedback clock using a window detection circuit after the internal voltage is stabilized, and performing a re-locking operation in the delay locked loop circuit using a dynamic delay control corresponding to the clock skew.
Claims19
A memory device comprising:
- a first delay line configured to delay a reference clock according to a first code value to output a first delayed clock;
- a second delay line configured to delay the first delayed clock according to a second code value to output a second delayed clock;
- a first delay line controller configured to generate the first code value according to a first phase difference value or to generate the first code value according to a second phase difference value;
- a second delay line controller configured to generate the second code value according to the second phase difference value;
- a de-multiplexer configured to output the second phase difference value to one of the first delay line controller and the second delay line controller, in response to a monitor detection signal corresponding to clock skew between the reference clock and a feedback clock;
- a first phase detector configured to detect the first phase difference value between the reference clock and the feedback clock;
- a second phase detector configured to detect the second phase difference value between the reference clock and the feedback clock;
- a clock path configured to receive the second delayed clock and configured to generate an internal clock;
- an output buffer configured to synchronize with the internal clock to output a data strobe signal;
- a clock path replica configured to delay the second delayed clock by a delay amount equal to a delay amount of the clock path;
- and
- an output buffer replica configured to delay a clock output from the clock path replica by a delay amount equal to a delay amount of the output buffer, to generate the feedback clock.
9 more elements
A clock locking method of a memory device, comprising:
- performing an initial locking operation in a delay locked loop circuit before an internal voltage is stabilized;
- monitoring clock skew between a reference clock and a feedback clock using a window detection circuit after the internal voltage is stabilized;
- and
- performing a re-locking operation in the delay locked loop circuit using a dynamic delay control corresponding to the clock skew.
1 more element
A memory device comprising:
- a memory cell array having a plurality of memory cells in which a plurality of word lines and a plurality of bit lines intersect;
- a row decoder configured to select one of the plurality of word lines in response to a row address;
- a bit line detection amplifier circuit configured to detect and amplify data from memory cells connected to selected bit lines, among the plurality of bit lines, during a read operation;
- a column decoder configured to select the selected bit lines, among the plurality of bit lines, in response to a column address;
- a data input/output device configured to receive data from the bit line detection amplifier circuit during the read operation, and to output the received data to an external device in response to a data strobe signal synchronized with an internal clock;
- a delay locked loop circuit configured to receive a reference clock and to generate the internal clock;
- and
- a window detection circuit configured to generate a monitor detection signal corresponding to clock skew between the reference clock and a feedback clock, wherein the window detection circuit is activated in response to an internal voltage stabilization signal.
5 more elements
Dependencies are inferred from the claim text.