Multi-level program pulse for programming single level memory cells to reduce damage

A method, comprising:

• initiating a program operation for memory cells connected to a selected word line, the memory cells are in a block and the block is configured to alternate between storing data in a single bit per cell mode and a multiple bits per cell mode;
• when the memory cells are to be programmed in a single bit per cell mode in the program operation, performing a respective first program-verify iteration of the program operation, the performing the respective first program-verify iteration comprises ramping up a voltage of the selected word line from an initial level to a pass level, from the pass level to a first program level, and from the first program level to a second program level;
• and
• when the memory cells are to be programmed in a multiple bits per cell mode in the program operation, performing a respective first program-verify iteration of the program operation, the performing the respective first program-verify iteration comprises ramping up the voltage of the selected word line from the initial level to the pass level, and from the pass level directly to a peak level which is less than the first program level.

An apparatus, comprising:

• a control circuit configured to connect to a set of memory cells, the set of memory cells comprise memory cells connected to a selected word line;
• and
• an interface connected to the control circuit, the control circuit is configured to issue a command via the interface to:
• perform an initial program-verify iteration of a program operation, wherein to perform the initial program-verify iteration, the control circuit is configured to bias the memory cells with a first control gate-to-drain voltage followed by a second control gate-to-drain voltage which is higher than the first control gate-to-drain voltage, followed by performing a verify test for the memory cells connected to the selected word line, the first control gate-to-drain voltage and the second control gate-to-drain voltage are configured to induce programming of the memory cells connected to the selected word line.