Memory device and operating method thereof

A memory device comprising:

• a plurality of memory cells;
• a plurality of page buffers each coupled to corresponding memory cells through a plurality of bit lines, and configured to temporarily store data in respective ones of the plurality of memory cells;
• and
• a page buffer controller configured to control one or more voltages to be applied to the plurality of bit lines in a program operation of storing the data in the plurality of memory cells, wherein
• the program operation includes a plurality of program loops, each including a program voltage apply operation and a verify operation,
• the program voltage apply operation includes a precharge period, a program voltage apply period, and a discharge period,
• the plurality of page buffers are configured to provide a bit line voltage to the plurality of bit lines in response to a page buffer sensing signal output from the page buffer controller, and
• the page buffer controller includes:
• a first signal provider configured to provide a first pulse signal as the page buffer sensing signal during a first period in the precharge period, the first pulse signal having a first voltage level higher than a ground voltage;
• and
• a second signal provider configured to provide a step signal as the page buffer sensing signal after the first period, the step signal increasing from the first voltage level to a second voltage level based on a step voltage, the step voltage corresponding to a loop count of the plurality of program loops among a plurality of predetermined step voltages.

A method for operating a memory device, the method comprising:

• providing a first pulse signal to a page buffer during a first period, the first pulse signal serving as a page buffer sensing signal and having a first voltage level higher than a ground voltage;
• providing the page buffer with a ramp signal after the first period, the ramp signal serving as the page buffer sensing signal and increasing from the first voltage level to a second voltage level with a slope determined based on a loop count of a plurality of program loops, the slope corresponding to one of a plurality of predetermined slopes;
• providing the page buffer with a second pulse signal after the ramp signal reaches the second voltage level, the second pulse signal serving as the page buffer sensing signal and having a third voltage level higher or equal to the second voltage level;
• and
• applying a program voltage to a word line commonly connected to a plurality of memory cells.

A memory device comprising:

• a plurality of memory cells;
• a voltage generator configured to generate operating voltages for a program operation of storing data in the plurality of memory cells;
• a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines, the plurality of page buffers providing a bit line voltage to the plurality of bit lines in response to a page buffer sensing signal;
• and
• a page buffer controller configured to provide the page buffer sensing signals to the plurality of page buffers in the program operation, wherein the page buffer controller includes:
• a first signal provider configured to provide a pulse signal as the page buffer sensing signal during a first period, the pulse signal generated by the voltage generator;
• and
• a second signal provider configured to provide a ramp signal as the page buffer sensing signal during a second period after the first period, the ramp signal having a slope determined based on a loop count of a program loop which represents a degree to which the program operation is performed, and
• the second signal provider including
• a plurality of switches provided with a page buffer pump voltage;
• a plurality of transistors grouped and connected in series to the plurality of switches, the plurality of transistors configured to output a bias current from the plurality of switches in response to a voltage control signal, the voltage control signal provided based on the loop count of the program loop;
• a capacitor commonly connected to the plurality of transistors and configured to charge a capacitor voltage with respect to the bias current;
• and
• a voltage output circuit commonly connected to the plurality of transistors and configured to transfer a capacitor voltage corresponding to the page buffer sensing signal.