Memory device and error correction method in memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWin-San Khwa
Life of this patent
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Abstract
A memory device and a method of correcting error in a memory device is provided. The memory device controller includes a memory array, a tie-breaker array, a write controller, a verify circuit, and a controller. The memory array includes a plurality of memory cells. The tie-breaker array includes a plurality of tie-breaker rows. The write controller is configured to apply a programming voltage to the memory array. The verify circuit is configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not. The controller is configured to enable one or more tie-breaker rows in additions to the memory array to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.
Claims20
A memory device comprising:
- a memory array, comprising a plurality of memory cells and a plurality of bit lines, each of the bit lines being connected to a set of the plurality of memory cells;
- a tie-breaker array, comprising a plurality of tie-breaker rows, each of the plurality of tie-breaker rows comprising a row of memory cells;
- a write controller, configured to apply a programming voltage to the memory array;
- a verify circuit, configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not;
- and
- a controller, configured to enable one or more of the tie-breaker rows to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state, wherein the controller is configured to set the memory cell in the enabled one or more of the tie-breaker rows that is connected to the bit line with a flipped bit to adjust the output of the bit line with the flipped bit.
A memory device comprising:
- a memory array, comprising a plurality of memory cells;
- a reference array, configured to generate a verify voltage in accordance with a plurality of inputs to the memory array;
- a tie-breaker array, comprises a plurality of tie-breaker rows;
- a write controller, configured to apply a programming voltage to the memory array;
- a verify circuit, configured to apply the verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not;
- and
- a controller, configured to enable one or more of the tie-breaker rows disposed in addition to the memory array to adjust the verify voltage generated by the reference array so as to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.
A method comprising:
- generating a verify voltage for verifying a plurality of memory cells in a memory array are in an unambiguous state or an ambiguous state;
- establishing a first output voltage by applying a first voltage to a first bit line of memory cells of the memory array;
- establishing a second output voltage by applying a second voltage to a second bit line of memory cells of the memory array;
- identifying the ambiguous state between the first output voltage and the second output voltage by applying the verify voltage;
- and
- transitioning the ambiguous state to the unambiguous state by adjusting the first output voltage, the second output voltage or the verify voltage by enabling at least one memory cell of at least one tie-breaker row of memory cells disposed outside the memory array.
Dependencies are inferred from the claim text.