Semiconductor memory device

Abstract

A semiconductor memory device of embodiments includes: a memory cell array including a plurality of memory cells; and a control circuit controlling an operation of each of the memory cells and including a first capacitor. The first capacitor includes: a semiconductor substrate having a first face and a second face facing the first face and including a first semiconductor region of p-type, a second semiconductor region of n-type provided between the first face and the first semiconductor region, and a third semiconductor region of p-type provided between the first face and the second semiconductor region and electrically connected to the first semiconductor region; a first electrode electrically connected to the second semiconductor region; and a first insulating film provided between the third semiconductor region and the first electrode.

Dependencies are inferred from the claim text.