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US 11,456,032 B2Granted
Systems and methods for memory cell accesses
AssigneeMicron Technology, Inc.
InventorYen Chun Lee
Life of this patent
Estimating the term…
Abstract
A memory device includes a plurality of memory elements. The memory device additionally includes a first current mirror that when in operation selectively outputs a first current to select a target memory cell as a first memory element of the plurality of memory elements. The memory device further includes a second current mirror that when in operation selectively outputs a second current to select the target memory cell as the first memory element of the plurality of memory elements.
Claims22
A memory device comprising:
- a memory array comprising a plurality of memory elements;
- a first circuit that when in operation selectively applies a first voltage to a word line of the memory array to select a target memory cell as a first memory element of the plurality of memory elements when the target memory cell is at a first location in the memory array, wherein the first circuit comprises a first current mirror;
- and
- a second circuit that when in operation selectively applies a second voltage to the word line of the memory array to select the target memory cell as the first memory element of the plurality of memory elements when the target memory cell is at a second location in the memory array, wherein the second circuit comprises a second current mirror.
1 more element
A memory device, comprising:
- a memory array comprising a plurality of memory elements organized into word lines and bit lines;
- a snap detection circuit coupled to the word lines of the memory array, wherein the snap detection circuit in operation detects a snap in a target memory cell;
- a first circuit that when in operation selectively applies a voltage to a first word line of the word lines in conjunction with a selection operation to select the target memory cell of the word line as a first memory element of the plurality of memory elements;
- a second circuit that when in operation selectively applies a second voltage to the first word line of the memory array in conjunction with the selection operation to select the target memory cell of the word line as the first memory element of the plurality of memory elements;
- and
- a control circuit comprising a first input coupled to the snap detection circuit and an output coupled to the first circuit and the second circuit.
3 more elements
A method comprising:
- determining a physical location of a target memory cell in a word line of a memory array;
- applying a first voltage from a first circuit to the word line at a first time in conjunction with a selection operation to select the target memory cell when the physical location is determined to have a first characteristic;
- applying a second voltage from a second circuit to the word line at the first time in conjunction with the selection operation to select the target memory cell when the physical location is determined to have a second characteristic;
- and
- detecting a snap of the target memory cell when the snap of the target memory cell occurs.
2 more elements
Dependencies are inferred from the claim text.