Distributed grouped terminations for multiple memory integrated circuit systems

An apparatus, comprising:

• a stack of uniform memory dies coupled to a transmission line by a set of wire bonds that connect each uniform memory die of the stack of uniform memory dies in series to form a transmission path;
• each uniform memory die of the stack of uniform memory dies comprising:
• an on-die termination resistance circuit configured to connect to the transmission line when a uniform memory die is powered on, the on-die termination resistance circuit comprising a programmable resistance circuit configured to provide a termination resistance during transmission of a data signal to a target uniform memory die;
• and
• a storage controller configured to:
• send a storage command to a target uniform memory die of the stack of uniform memory dies for an operation;
• direct at least four uniform memory die along the transmission path to provide termination resistance during a portion of the operation, the at least four uniform memory die different from the target uniform memory die;
• and
• transmit a plurality of data signals for the operation to the target uniform memory die with the at least four uniform memory die generating an effective termination resistance for the transmission path during the operation.

A method, comprising:

• sending a storage command to a target uniform memory die of a stack of uniform memory dies for an operation, the stack of uniform memory dies connected in series to a transmission line by wire bonds to form a transmission path;
• activating an on-die termination resistance circuit of at least four adjacent uniform memory die along the transmission path to provide an effective termination resistance lower than a minimum termination resistance of each of the on-die termination resistance circuits individually, the at least four uniform memory die different from the target uniform memory die;
• and
• transmitting data signals for the operation to the target uniform memory die with the at least four uniform memory die providing parallel termination resistance during the operation.