Shift register circuit with latch potential and its driving method, display panel, and display device

A driving method for a shift register circuit, comprising a first stage, a second stage, and a third stage performed sequentially, wherein:

• the shift register circuit includes an input module, a first inverter, a second inverter, and an output module;
• the input module is electrically connected to a first input terminal, a second input terminal, a third input terminal, and a first electrical-level terminal, and is configured to respond to signals from the second input terminal and the third input terminal to control a potential of a first node;
• an input terminal of the first inverter is electrically connected to the first node, and an output terminal of the first inverter is electrically connected to a second node;
• an input terminal of the second inverter is electrically connected to the second node, and an output terminal of the second inverter is electrically connected to the first node;
• and
• the output module is configured to respond to a potential of the first node to provide a signal of a fourth input terminal to an output terminal of the output module, and is also configured to respond to a potential of the second node to provide a voltage of a first power terminal to the output terminal of the output module,
• wherein:
• the input module includes a first transistor,
• a first terminal of the first transistor is electrically connected to the first input terminal,
• a gate of the first transistor is electrically connected to the second input terminal,
• a second terminal of the first transistor is electrically connected to the first node, and
• a width-length ratio of the first transistor is larger than a width-length ratio of one transistor of transistors in the second inverter connected to an electrical-level signal opposite to an enable signal outputted by the first input terminal;
• in the first stage, the input module controlling the first input terminal to be connected to the first node in response to the signal of the second input terminal, and the output module controlling the fourth input terminal to be connected to the output terminal of the output module in response to the signal of the first node;
• in the second stage, the output module maintaining a control of the fourth input terminal to be connected to the output terminal of the output module in response to the signal of the first node;
• and
• in the third stage, the input module controlling the first electrical-level terminal to be connected to the first node in response to the signal of the third input terminal, and the output module controlling the first power terminal to be connected to the output terminal of the output module in response to the signal of the second node.

A display panel comprising a scanning driving circuit, wherein:

• the scanning driving circuit includes multi-level shift register circuits;
• each shift register circuit of the multi-level shift register circuits includes an input module, a first inverter, a second inverter, and an output module;
• the input module is electrically connected to a first input terminal, a second input terminal, a third input terminal, and a first electrical-level terminal, and is configured to respond to signals from the second input terminal and the third input terminal to control a potential of a first node;
• an input terminal of the first inverter is electrically connected to the first node, and an output terminal of the first inverter is electrically connected to a second node;
• an input terminal of the second inverter is electrically connected to the second node, and an output terminal of the second inverter is electrically connected to the first node;
• and
• the output module is configured to respond to a potential of the first node to provide a signal of a fourth input terminal to an output terminal of the output module, and is also configured to respond to a potential of the second node to provide a voltage of a first power terminal to the output terminal of the output module,
• wherein:
• the input module includes a first transistor,
• a first terminal of the first transistor is electrically connected to the first input terminal,
• a gate of the first transistor is electrically connected to the second input terminal,
• a second terminal of the first transistor is electrically connected to the first node, and
• a width-length ratio of the first transistor is larger than a width-length ratio of one transistor of transistors in the second inverter connected to an electrical-level signal opposite to an enable signal outputted by the first input terminal;
• the multi-level shift register circuits are arranged in cascade, and includes a first level shift register circuit to an N-th level shift register circuit, wherein N is an integer larger than or equal to 3;
• the scanning driving circuit further includes a turn-on signal line, a first clock signal line, a second clock signal line, and a third clock signal line;
• a first input terminal and a second input terminal of the first-level shift register circuit are both electrically connected to the turn-on signal line;
• except for the first-level shift register circuit, a first input terminal and a second input terminal of each level shift register circuit are both electrically connected to the output terminal of the output module of a previous level shift register circuit;
• for an i-th level shift register circuit, a third input terminal thereof is electrically connected to the second clock signal line, and a fourth input terminal is electrically connected to the first clock signal line;
• for an (i+1)-th level shift register circuit, a third input terminal thereof is electrically connected to the third clock signal line and a fourth input terminal is electrically connected to the second clock signal line;
• for an (i+2) level shift register circuit, a third input terminal thereof is electrically connected to the first clock signal line and a fourth input terminal thereof is electrically connected to the third clock signal line;
• i=3n+1, wherein n is an integer larger than or equal to 0, and i+2 is a positive integer less than N;
• and
• the enable signal segments of the first clock signal line, the second clock signal line, and the third clock signal line are sequentially arranged in time.

A display device, comprising a display panel, wherein:

• the display panel including a scanning driving circuit;
• the scanning driving circuit includes multi-level shift register circuits;
• each shift register circuit of the multi-level shift register circuits includes an input module, a first inverter, a second inverter, and an output module;
• the input module is electrically connected to a first input terminal, a second input terminal, a third input terminal, and a first electrical-level terminal, and is configured to respond to signals from the second input terminal and the third input terminal to control a potential of a first node;
• an input terminal of the first inverter is electrically connected to the first node, and an output terminal of the first inverter is electrically connected to a second node;
• an input terminal of the second inverter is electrically connected to the second node, and an output terminal of the second inverter is electrically connected to the first node;
• and
• the output module is configured to respond to a potential of the first node to provide a signal of a fourth input terminal to an output terminal of the output module, and is also configured to respond to a potential of the second node to provide a voltage of a first power terminal to the output terminal of the output module,
• wherein:
• the input module includes a first transistor,
• a first terminal of the first transistor is electrically connected to the first input terminal,
• a gate of the first transistor is electrically connected to the second input terminal,
• a second terminal of the first transistor is electrically connected to the first node, and
• a width-length ratio of the first transistor is larger than a width-length ratio of one transistor of transistors in the second inverter connected to an electrical-level signal opposite to an enable signal outputted by the first input terminal;
• the multi-level shift register circuits are arranged in cascade, and includes a first level shift register circuit to an N-th level shift register circuit, wherein N is an integer larger than or equal to 3;
• the scanning driving circuit further includes a turn-on signal line, a first clock signal line, a second clock signal line, and a third clock signal line;
• a first input terminal and a second input terminal of the first-level shift register circuit are both electrically connected to the turn-on signal line;
• except for the first-level shift register circuit, a first input terminal and a second input terminal of each level shift register circuit are both electrically connected to the output terminal of the output module of a previous level shift register circuit;
• for an i-th level shift register circuit, a third input terminal thereof is electrically connected to the second clock signal line, and a fourth input terminal is electrically connected to the first clock signal line;
• for an (i+1)-th level shift register circuit, a third input terminal thereof is electrically connected to the third clock signal line and a fourth input terminal is electrically connected to the second clock signal line;
• for an (i+2) level shift register circuit, a third input terminal thereof is electrically connected to the first clock signal line and a fourth input terminal thereof is electrically connected to the third clock signal line;
• i=3n+1, wherein n is an integer larger than or equal to 0, and i+2 is a positive integer less than N;
• and
• the enable signal segments of the first clock signal line, the second clock signal line, and the third clock signal line are sequentially arranged in time.