Shift register and drive method therefor, and gate drive circuit
AssigneesHefei BOE Joint Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
InventorsXuehuan Feng, Yongqian Li
Life of this patent
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Abstract
A shift register and a drive method therefor, and a gate drive circuit. The shift register includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit. The detection control sub-circuit is respectively connected to a random detection signal end (OE), a signal input end (INPUT), a first clock signal end (CLKA), a first reset end (RST1), and a pull-up node (PU), and is configured to provide a signal of the first clock signal end (CLKA) for the pull-up node (PU) under the control of the signal input end (INPUT), the random detection signal end (OE), the first clock signal end (CLKA), and the first reset end (RST1).
Claims15
A shift register, comprising:
- an input sub-circuit, a sensing control sub-circuit, an output sub-circuit, a first reset sub-circuit and a pull-down sub-circuit;
- the input sub-circuit is connected with a signal input terminal, a first power supply terminal and a pull-up node respectively, and is configured to provide a signal of the first power supply terminal to the pull-up node under control of the signal input terminal;
- the sensing control sub-circuit is connected with a random sensing signal terminal, the signal input terminal, a first clock signal terminal, a first reset terminal and the pull-up node respectively and is configured to provide a signal of the first clock signal terminal to the pull-up node under control of the signal input terminal, the random sensing signal terminal, the first clock signal terminal and the first reset terminal;
- the first reset sub-circuit is connected with the first reset terminal, the pull-up node and a second power supply terminal respectively, and is configured to provide a signal of the second power supply terminal to the pull-up node under control of the first reset terminal;
- the output sub-circuit is connected with a second clock signal terminal, a third clock signal terminal, the pull-up node, a first output terminal and a second output terminal respectively, and is configured to provide a signal of the third clock signal terminal to the first output terminal and provide a signal of the second clock signal terminal to the second output terminal under control of the pull-up node;
- and
- the pull-down sub-circuit is connected with the first power supply terminal, the second power supply terminal, a third power supply terminal, the pull-up node, the first output terminal and the second output terminal respectively, and is configured to provide the signal of the second power supply terminal to the pull-up node and the second output terminal, and provide a signal of the third power supply terminal to the first output terminal under control of the first power supply terminal and the pull-up node.
Dependencies are inferred from the claim text.