System and method for LCD display panel failure diagnostics

A method of detecting failure in a liquid crystal display (LCD) device, the method comprising:

• providing, in an LCD panel of the LCD display, a first plurality of pixel data inputs and a first failure sensing circuit, wherein the first pixel data inputs are each coupled to associated columns of first pixel elements, and wherein the first failure sensing circuit is configured to provide a first failure indication on a first output of the LCD panel;
• driving, by a first source driver of the LCD device, first pixel data onto the first pixel data inputs;
• providing, by a timing controller of the LCD device coupled to the first source driver by a pixel data link, the first pixel data to the first source driver via the pixel data link;
• driving, by the first source driver in a first test mode, a first voltage onto all of the first pixel data inputs;
• providing, in the first test mode, the first voltage on the first output when the LCD panel has no failures on any of the first pixel elements;
• providing, in the first test mode, any other second voltage when the LCD panel has at least one failing first pixel element, wherein the at least one failing first pixel element is in a high impedance state;
• initiating, by the timing controller in a second test mode, a pixel data link test signal via the pixel data link;
• and
• providing, by the first source driver in the second test mode, a second failure indication indicating a failure on the pixel data link.

An information handling system, comprising:

• a processor;
• and
• a liquid crystal display (LCD) device including:
• an LCD panel including a first plurality of pixel data inputs and a first failure sensing circuit, wherein the first pixel data inputs are each coupled to associated columns of first pixel elements, and wherein the first failure sensing circuit is configured to provide a first failure indication on a first output of the LCD panel;
• a first source driver configured to drive first pixel data onto the first pixel data inputs, wherein, in a first test mode, the first source driver is configured to drive a first voltage onto all of the first pixel data inputs;
• and
• a timing controller coupled to the first source driver by a pixel data link, the timing controller configured to provide the first pixel data to the first source driver via the pixel data link;
• wherein, in the first test mode, the first failure indication includes the first voltage when the LCD panel has no failures on any of the first pixel elements, and the first failure indication includes any other second voltage when the LCD panel has at least one failing first pixel element, wherein the at least one failing first pixel element is in a high impedance state;
• wherein the processor directs the LCD device to enter the first test mode;
• and
• wherein in a second test mode, the timing controller is configured to initiate a pixel data link test signal via the pixel data link, and the first source driver is further configured to provide a second failure indication indicating a failure on the pixel data link.