Electromagnetic characteristic extraction of large-scale integrated circuits

A computer-implemented system for generating a digital simulation model of a large-scale integrated circuit, the computer-implemented system comprising:

• one or more data processors;
• one or more computer-readable storage mediums encoded with instructions for commanding the one or more data processors to execute steps that include:
• receiving an input layout of the large-scale integrated circuit, the input layout comprising a netlist having a plurality of segments;
• identifying groups of segments from the plurality of segments based on a numerical magnetic coupling factor;
• generating a plurality of matrices comprising a conductance matrix, a capacitance matrix, and an inductance matrix, wherein submatrices of the inductance matrix are based on the groups of segments, and wherein generating the plurality of submatrices comprises
• (i) generating an inductance submatrix for each group of the groups of segments, wherein the inductance submatrix includes a full-rank representation of each group of the groups of segments,
• (ii) generating a mutual inductance submatrix for pairs of the groups of segments, wherein the mutual inductance submatrix includes a low-rank approximation of each pair of the groups of segments, and
• (iii) generating a hierarchical inductance matrix by combining together the inductance submatrix and the mutual inductance submatrix, wherein the hierarchical inductance matrix is an inductance matrix;
• generating a plurality of reduced-order matrices by performing model-order reduction on the conductance matrix, the capacitance matrix, and the hierarchical inductance matrix to reduce a memory requirement or reduce a computation cost;
• and
• outputting a reduced-order simulation model based on the plurality of reduced-order matrices for computer simulation of the large-scale integrated circuit.

A non-transitory computer-readable storage medium comprising instructions for which when executed cause a processing system to execute steps comprising:

• receiving an input layout of the large-scale integrated circuit, the input layout comprising a netlist having a plurality of segments;
• identifying groups of segments from the plurality of segments based on a numerical magnetic coupling factor;
• generating a plurality of matrices comprising a conductance matrix, a capacitance matrix, and an inductance matrix, wherein submatrices of the inductance matrix are based on the groups of segments, and wherein generating the plurality of submatrices comprises
• (i) generating an inductance submatrix for each group of the groups of segments, wherein the inductance submatrix includes a full-rank representation of each group of the groups of segments,
• (ii) generating a mutual inductance submatrix for pairs of the groups of segments, wherein the mutual inductance submatrix includes a low-rank approximation of each pair of the groups of segments, and
• (iii) generating a hierarchical inductance matrix by combining together the inductance submatrix and the mutual inductance submatrix, wherein the hierarchical inductance matrix is an inductance matrix;
• generating a plurality of reduced-order matrices by performing model-order reduction on the conductance matrix, the capacitance matrix, and the hierarchical inductance matrix to reduce a memory requirement or reduce a computation cost;
• and
• outputting a reduced-order simulation model based on the plurality of reduced-order matrices for computer simulation of the large-scale integrated circuit.