Predicting across wafer spin-on planarization over a patterned topography
AssigneeTokyo Electron Limited
InventorsRyan Burns, Mark Somervell
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AssigneeTokyo Electron Limited
InventorsRyan Burns, Mark Somervell
Estimating the term…
Methods used to more accurately predict spin on layer planarization over a patterned topography are provided. Methods are provided for generating a layer critical dimension model. In one embodiment, the critical dimension model is a layer thickness model that more accurately simulates patterned topography trends, as a function of feature dimensions, surrounding pattern density and radial position across the patterned topography. Additional methods are provided for calibrating the layer thickness model over one or more spatial areas to account for radial variations in the patterned topography. Further methods are provided for using one or more calibrated layer thickness models to predict a thickness of a layer (e.g., a spin on coating) as it is being deposited onto a patterned substrate. The methods disclosed herein may facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar layer or layer on the substrate.
A method for predicting a critical dimension of a layer being deposited onto a patterned substrate as part of a fabrication process, the method comprising:
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