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US 11,455,371 B2Granted
Computation circuit for performing vector-matrix multiplication and semiconductor device including the computation circuit
AssigneesSK hynix Inc., Donguk Lee
InventorDonguk Lee
Life of this patent
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Abstract
A computation circuit includes a computing cell array configured to provide a plurality of physical values respectively corresponding to a plurality of elements of a matrix; a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array; and a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances.
Claims17
A computation circuit comprising:
- a computing cell array configured to provide a plurality of effective capacitances respectively corresponding to a plurality of elements of a matrix;
- a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array;
- and
- a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances,
- wherein the computing cell array comprises:
- a plurality of computing cells;
- a plurality of plate lines;
- and
- a plurality of bit lines,
- wherein each of the plurality of computing cells is located where a respective one of the plurality of plate lines and a respective one of the plurality of the bit lines cross,
- wherein each of the plurality of computing cells includes a plurality of capacitors selectively coupled between the respective one of the plurality of plate lines and the respective one of the plurality of bit lines;
- and
- wherein an effective capacitance between the respective one of the plurality of plate lines and the respective one of the plurality of bit lines respectively corresponds to a value of an element included in the matrix.
10 more elements
A semiconductor device comprising:
- a command decoder configured to receive a command and an address;
- a data input/output (IO) buffer configured to input or output data according to a control of the command decoder;
- and
- a computation circuit configured to generate a plurality of output voltages corresponding to product of an input vector provided from the data IO buffer and a matrix according to a control of the command decoder,
- wherein the computation circuit comprises:
- a computing cell array configured to set and store a plurality of effective capacitances respectively corresponding to the elements of the matrix;
- a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array;
- and
- a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances,
- wherein the computing cell array comprises:
- a plurality of computing cells;
- a plurality of plate lines;
- and
- a plurality of bit lines,
- wherein each of the plurality of computing cells is located where one of the plurality of plate lines and one of the plurality of the bit lines cross,
- wherein each of the plurality of computing cells includes a plurality of capacitors selectively coupled between one of the plurality of plate lines and one of the plurality of bit lines;
- and
- wherein an effective capacitance between one of the plurality of plate lines and one of the plurality of bit lines corresponds to a value of an element included in the matrix.
15 more elements
Dependencies are inferred from the claim text.