MAC processing pipeline having conversion circuitry, and methods of operating same

An integrated circuit comprising:

• a multiplier-accumulator execution pipeline to receive (i) image data and (ii) filter weights, wherein the multiplier-accumulator execution pipeline includes a plurality of multiplier-accumulator circuits to process the image data, using associated filter weights, via a plurality of multiply and accumulate operations;
• first conversion circuitry, coupled to an input of the multiplier-accumulator execution pipeline, wherein the first conversion circuitry includes:
• inputs to receive image data of a plurality of sets of image data, wherein each set of image data includes a plurality of image data, wherein the image data of each set of image data of the plurality of sets of image data includes a floating point data format,
• block scaled fraction conversion circuitry, coupled to the inputs of the first conversion circuitry, to convert the image data of each set of image data of the plurality of sets of image data to a block scaled fraction (BSF) data format,
• Winograd conversion circuitry, coupled to the block scaled fraction conversion circuitry and configured to (i) receive the image data of each set of image data of the plurality of sets of image data having the block scaled fraction (BSF) data format and (ii) convert each set of image data of the plurality of sets of image data to a corresponding Winograd set of image data, wherein:
• the image data of each set of image data of the plurality of sets of image data converted to the corresponding Winograd set of image data via the Winograd conversion circuitry includes the block scaled fraction (BSF) data format,
• floating point format conversion circuitry, coupled to the Winograd conversion circuitry of the first conversion circuitry, to (i) receive the image data of each Winograd set of image data of the plurality of Winograd sets of image data and (ii) convert the image data of each Winograd set of image data of the plurality of Winograd sets of image data to a floating point data format, and
• outputs to output the image data of the plurality of Winograd sets of image data to the multiplier-accumulator execution pipeline, wherein the image data of each Winograd set of image data includes the floating point data format;
• second conversion circuitry, coupled an input of the multiplier-accumulator execution pipeline, wherein the second conversion circuitry includes:
• inputs to receive filter weights of a plurality of sets of filter weights, wherein each set of filter weights includes a plurality of filter weights,
• Winograd conversion circuitry to convert each set of filter weights of the plurality of sets of filter weights to a corresponding Winograd set of filter weights of a plurality of Winograd sets of filter weights,
• floating point format conversion circuitry, coupled to the Winograd conversion circuitry of the second conversion circuitry, to (i) receive the filter weights of each Winograd set of filter weights and (ii) convert the filter weights of each Winograd set of filter weights of the plurality of Winograd sets of filter weights to a floating point data format, and
• outputs to output the filter weights of each Winograd set of filter weights of the plurality of Winograd sets of filter weights to the multiplier-accumulator execution pipeline, wherein the filter weights of each Winograd set of image data includes the floating point data format;
• and
• wherein, in operation, the multiplier-accumulator circuits of the multiplier-accumulator execution pipeline are configured to:
• (i) perform the plurality of multiply and accumulate operations using (a) the image data, having the floating point data format, of the plurality of Winograd sets of image data that are output from the first conversion circuitry and (b) the filter weights, having the floating point data format, of each Winograd set of filter weights of the plurality of Winograd sets of filter weights, and (ii) generate output data of a plurality of sets of output data based on the plurality of multiply and accumulate operations.

An integrated circuit comprising:

• a multiplier-accumulator execution pipeline to receive (i) image data and (ii) filter weights, wherein the multiplier-accumulator execution pipeline includes a plurality of multiplier-accumulator circuits to process the image data, using associated filter weights, via a plurality of multiply and accumulate operations;
• first conversion circuitry, coupled to an input of the multiplier-accumulator execution pipeline, wherein the first conversion circuitry includes:
• inputs to receive image data of a plurality of sets of image data, wherein each set of image data includes a plurality of image data, wherein the image data of each set of image data of the plurality of sets of image data includes a floating point data format,
• block scaled fraction conversion circuitry, coupled to the inputs of the first conversion circuitry, to convert the image data of each set of image data of the plurality of sets of image data to a block scaled fraction (BSF) data format,
• Winograd conversion circuitry, coupled to the block scaled fraction conversion circuitry and configured to (i) receive the image data of each set of image data of the plurality of sets of image data having the block scaled fraction (BSF) data format and (ii) convert each set of image data of the plurality of sets of image data to a corresponding Winograd set of image data, wherein:
• the image data of each set of image data of the plurality of sets of image data converted to the corresponding Winograd set of image data via the Winograd conversion circuitry includes the block scaled fraction (BSF) data format,
• floating point format conversion circuitry, coupled to the Winograd conversion circuitry of the first conversion circuitry, to (i) receive the image data of each Winograd set of image data of the plurality of Winograd sets of image data and (ii) convert the image data of each Winograd set of image data of the plurality of Winograd sets of image data to a floating point data format, and
• outputs to output the image data of the plurality of Winograd sets of image data to the multiplier-accumulator execution pipeline, wherein the image data of each Winograd set of image data includes the floating point data format;
• second conversion circuitry, coupled an input of the multiplier-accumulator execution pipeline, wherein the second conversion circuitry includes:
• inputs to receive filter weights of a plurality of sets of filter weights, wherein each set of filter weights includes a plurality of filter weights,
• Winograd conversion circuitry to convert each set of filter weights of the plurality of sets of filter weights to a corresponding Winograd set of filter weights of a plurality of Winograd sets of filter weights,
• floating point format conversion circuitry, coupled to the Winograd conversion circuitry of the second conversion circuitry, to (i) receive the filter weights of each Winograd set of filter weights and (ii) convert the filter weights of each Winograd set of filter weights of the plurality of Winograd sets of filter weights to a floating point data format, and
• outputs to output the filter weights of each Winograd set of filter weights of the plurality of Winograd sets of filter weights to the multiplier-accumulator execution pipeline, wherein the filter weights of each Winograd set of image data includes the floating point data format;
• wherein, in operation, the multiplier-accumulator circuits of the multiplier-accumulator execution pipeline are configured to:
• (i) perform the plurality of multiply and accumulate operations using (a) the image data, having the floating point data format, of the plurality of Winograd sets of image data that are output from the first conversion circuitry and (b) the filter weights, having the floating point data format, of each Winograd set of filter weights of the plurality of Winograd sets of filter weights, and (ii) generate output data of a plurality of sets of output data based on the plurality of multiply and accumulate operations;
• and
• third conversion circuitry, coupled an output of the multiplier-accumulator execution pipeline, wherein the third conversion circuitry includes:
• inputs to receive the output data of the plurality of sets of output data from the multiplier-accumulator circuits of the multiplier-accumulator execution pipeline,
• Winograd conversion circuitry to convert each set of output data of the plurality of sets of output data to a corresponding non-Winograd set of output data,
• floating point format conversion circuitry, coupled to the Winograd conversion circuitry of the third conversion circuitry, to convert the output data of each non-Winograd set of output data to a floating point data format, and
• outputs to output the output data, having a floating point data format, of the plurality of sets of output data from the floating point format conversion circuitry of the third conversion circuitry.