Multimedia application processor architecture

A multimedia application processor architecture, comprising a master control system, at least two groups of independent multimedia application processors, at least two groups of common CPU, a power manager, and a common interface and CPU bus, wherein the master control system is connected to each group of the independent multimedia application processors, each group of the common CPU, the power manager, and the common interface and CPU bus respectively, and is configured to control and manage, and provide power control and management for, the at least two groups of independent multimedia application processors, the at least two groups of common CPU, the power manager, and the common interface and CPU bus, each group of the common CPU is connected to the independent multimedia application processors for providing a backup central processor data processing capability for the independent multimedia application processors, each group of the independent multimedia application processors can independently process Wireless Fidelity (WIFI), Global Positioning System/BeiDou Navigation Satellite System (GPS/BDS) positioning, and one group of 5G or 6G modem signals, and multiple groups of the independent multimedia application processors can independently process WIFI, GPS/BDS positioning, and multiple groups of 5G or 6G modem signals, such that a device can simultaneously process multiple work tasks and needs in parallel;

• each group of the independent multimedia application processors comprises at least a CPU, a graphics processing unit (GPU), an audio processor, a video encoder+decoder (Video CODEC), a track and debug module (DMA module), a synchronous dynamic random access memory controller (SDRAM controller), a direct memory access module (DMA module), a flash memory, a universal asynchronous receiver/transmitter (UART), a serial peripheral interface (SPI), and a general purpose input/output port (GPIO);
• each group of the common CPU is composed of one group of common processors;
• when the CPU of the independent application processor itself reaches a limit of data processing capabilities, the master control system immediately requisitions the common CPU to join in a common data processing work task;
• when a first group of the common CPU requisitioned also reaches a limit of data processing capabilities, the master control system requisitions a second group of common CPU again to join in the data processing work task until the work need of cooperating with the independent multimedia application processors is met;
• and so on, such that the common CPU are managed to cooperate with the independent multimedia application processors to complete the work task;
• and when the work task is reduced, the master control system reduces the number of the common CPU requisitioned until the independent multimedia application processors can complete the data processing work task by themselves, in which case the common CPU are no longer requisitioned.