Inter-processor communication
AssigneeNordic Semiconductor ASA
InventorVille Meriö
Life of this patent
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Abstract
An electronic device comprises a first processor and a second processor. An inter-processor communication module is connected to the processors and comprises a high priority mailbox and a low priority mailbox. The first processor sends a high or low priority message to the second processor. The first processor is arranged such that if it has a high priority message to send to the second processor, the first processor places the high priority message in the high priority mailbox and sends an interrupt request to the second processor. However, when the first processor has a low priority message to send to the second processor, the first processor places the high priority message in the low priority mailbox to be checked later without sending an interrupt request to the second processor.
Claims16
An electronic device comprising:
- at least first and second processors;
- and
- an inter-processor communication module connected to said first and second processors, said inter-processor communication module comprising a first mailbox and a second mailbox;
- wherein the first processor is arranged to send a message to the second processor, said message being either a high priority message or a low priority message;
- wherein the second processor is operable in a normal power mode of operation and a low power mode of operation in which one or more functions of the second processor are disabled;
- and
- wherein the first processor is further arranged such that:
- when the first processor has a high priority message to send to the second processor, the first processor places the high priority message in the first mailbox and sends an interrupt request to the second processor;
- and
- when the first processor has a low priority message to send to the second processor, the first processor places the low priority message in the second mailbox, does not send an interrupt request to the second processor;
- and sets a low priority message waiting flag;
- wherein the second processor is arranged to check whether the low priority message waiting flag is set or to check the second mailbox after switching from the low power mode to the normal power mode;
- and
- wherein the inter-processor communication module is arranged to set a mailbox full flag when the number of messages contained in the second mailbox exceeds a threshold value, wherein setting the mailbox full flag sends an interrupt request to the second processor.
A method of operating an electronic device comprising at least first and second processors and an inter-processor communication module connected to said first and second processors, wherein the second processor is operable in a normal power mode of operation and a low power mode of operation in which one or more functions of the second processor are disabled, said inter-processor communication module comprising a first mailbox and a second mailbox, wherein the method comprises:
- determining when the first processor has a message to send to the second processor, wherein said message is a high priority message or a low priority message;
- when the first processor has a high priority message to send to the second processor, placing the high priority message in the first mailbox and sending an interrupt request to the second processor;
- and
- when the first processor has a low priority message to send to the second processor, placing the low priority message in the second mailbox, not sending an interrupt request to the second processor, and setting a low priority message waiting flag;
- the second processor checking whether the low priority message waiting flag is set or checking the second mailbox after switching from the low power mode to the normal power mode;
- and
- the inter-processor communication module setting a mailbox full flag when the number of messages contained in the second mailbox exceeds a threshold value, wherein setting the mailbox full flag sends an interrupt request to the second processor.
A non-transitory computer-readable medium that, when executed on a first processor, causes the first processor to execute a method of communicating with a second processor, wherein the second processor is operable in a normal power mode of operation and a low power mode of operation in which one or more functions of the second processor are disabled, wherein the method comprises:
- determining when the first processor has a message to send to the second processor, wherein said message is a high priority message or a low priority message;
- when the first processor has a high priority message to send to the second processor, placing the high priority message in a first mailbox within an inter-processor communication module connected to said first and second processors, and sending an interrupt request to the second processor;
- and
- when the first processor has a low priority message to send to the second processor, placing the low priority message in a second mailbox within the inter-processor communication module, not sending an interrupt request to the second processor, and setting a low priority message waiting flag;
- the second processor checking whether the low priority message waiting flag is set or checking the second mailbox after switching from the low power mode to the normal power mode;
- and
- wherein the inter-processor communication module setting a mailbox full flag when the number of messages contained in the second mailbox exceeds a threshold value, wherein setting the mailbox full flag sends an interrupt request to the second processor.
Dependencies are inferred from the claim text.