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US 11,455,262 B2Granted
Reducing latency for memory operations in a memory controller
AssigneeMicron Technology, Inc.
InventorTony Brewer
Life of this patent
Estimating the term…
Abstract
Disclosed in some examples are methods, systems, memory controllers, devices, and machine-readable mediums which minimize this stall time by returning a memory write acknowledgement once a write command has been selected by the memory controller input multiplexor rather than when the memory write command has been performed. Because the memory controller enforces an ordering to memory once the packet has been selected at an input multiplexor, ordering of prior and subsequent requests to the same address location are preserved and providing the response early allows the processor to continue its operations earlier without any harmful effects.
Claims20
An apparatus comprising:
- a memory array;
- a first input queue coupled to the memory array and configured to receive a memory request from a requesting processor;
- logic of a memory controller coupled to the first input queue and the memory array and configured to:
- select a memory request from the first input queue using an input multiplexor, the input multiplexor multiplexing between the first input queue and a second input queue, the selected memory request received from a requesting processor, the first input queue an input queue storing memory requests from the requesting processor that are received over a packet-based network-on-chip interface and the second input queue storing memory requests from a programmable atomic unit of the memory controller;
- determine that the memory request is a write request to write a request value to a requested location in a memory of the memory array;
- responsive to a determination that the memory request is a write request:
- send a response to the requesting processor over the packet-based network-on-chip interface, the response sent prior to performing the write request;
- after sending the response to the requesting processor, performing the write request to write the request value to the requested location in memory;
- and
- enforce an ordering of the write request such that a prior write request to the requested location is completed first and a subsequent write command to the requested location is completed after the write request.
7 more elements
A method comprising:
- at a memory controller:
- selecting a memory request from a first input queue using an input multiplexor, the input multiplexor multiplexing between the first input queue and a second input queue, the selected memory request received from a requesting processor, the first input queue an input queue storing memory requests from the requesting processor that are received over a packet-based network-on-chip interface and the second input queue storing memory requests from a programmable atomic unit of the memory controller
- determining that the memory request is a write request to write a request value to a requested location in a memory;
- responsive to determining that the memory request is a write request:
- sending a response to the requesting processor over the packet-based network-on-chip interface, the response sent prior to performing the write request;
- after sending the response to the requesting processor, performing the write request to write the request value to the requested location in memory;
- and
- enforce an ordering of the write request such that a prior write request to the requested location is completed first and a subsequent write command to the requested location is completed after the write request.
5 more elements
A non-transitory machine-readable medium, storing instructions, which when executed by a memory controller, causes the memory controller to perform operations comprising:
- selecting a memory request from a first input queue using an input multiplexor, the input multiplexor multiplexing between the first input queue and a second input queue, the selected memory request received from a requesting processor, the first input queue an input queue storing memory requests from the requesting processor that are received over a packet-based network-on-chip interface and the second input queue storing memory requests from a programmable atomic unit of the memory controller
- determining that the memory request is a write request to write a request value to a requested location in a memory;
- responsive to determining that the memory request is a write request:
- sending a response to the requesting processor over the packet-based network-on-chip interface, the response sent prior to performing the write request;
- after sending the response to the requesting processor, performing the write request to write the request value to the requested location in memory;
- and
- enforce an ordering of the write request such that a prior write request to the requested location is completed first and a subsequent write command to the requested location is completed after the write request.
4 more elements
Dependencies are inferred from the claim text.