Semiconductor device capable of performing software lock-step

A semiconductor device which performs a SoftWare Lock-Step (SWLS), comprising:

• a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory coupled to the first IP via the first bus;
• a second circuit group including a second IP to be operated in a second address space different from the first address space, a second bus, and a second memory coupled to the second IP via the second bus;
• a third bus connectable to a third memory;
• and
• a transfer control circuit coupled to the first to third buses, and including a comparator,
• wherein addresses assigned to the first memory in the first address space are different from addresses assigned to the second memory in the second address space,
• wherein the first memory is configured to be accessed using the addresses assigned to the first memory in the first address space,
• wherein the second memory is configured to be accessed using the addresses assigned to the second memory in the second address space,
• wherein, when the SWLS is performed,
• the transfer control circuit is configured to read a program for the SWLS from the third memory and to transfer the read program for the SWLS to the first and second memories,
• the first IP is configured to execute the program for the SWLS stored in the first memory to store a first execution result in the first memory,
• the second IP is configured to execute the program for the SWLS stored in the second memory to store a second execution result in the second memory,
• the transfer control circuit is configured to read the first and second execution results from the first and second memories, and compare the first execution result with the second execution result using the comparator, and
• the second circuit group is configured to convert an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space,
• wherein an address for data access written in the program for the SWLS corresponds to an address assigned to the first memory in the first address space,
• wherein the second bus comprises:
• an address conversion circuit configured to convert the access address from the second IP to the second memory;
• and
• an operation mode setting register configured to be set to any of a first value indicating that the SWLS is to be performed and a second value indicating that the SWLS is not to be performed,
• wherein, when the first value is set in the operation mode setting register, the address conversion circuit is configured to convert the access address from the second IP to the second memory such that the address assigned to the second memory in the second address space is the same as the address assigned to the first memory in the first address space, and
• wherein, when the second value is set in the operation mode setting register, the address conversion circuit is configured to not convert the access address from the second IP to the second memory.