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US 11,455,221 B2Granted
Memory with concurrent fault detection and redundancy
AssigneeQUALCOMM Incorporated
InventorPraveen Raghuraman
Life of this patent
Estimating the term…
Abstract
A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.
Claims23
A memory, comprising:
- an array of memory cells;
- an error detection circuit configured to detect an error in the array of memory cells and to identify a faulty feature within the array of memory cells containing the error, wherein the error detection circuit is configured to be active responsive to an assertion of a first mode signal and to be inactive responsive to a de-assertion of the first mode signal;
- a redundancy enable circuit configured to replace the faulty feature with a redundant feature, wherein the redundancy enable circuit is configured to be active responsive to an assertion of a second mode signal and to be inactive responsive to a de-assertion of the second mode signal;
- and
- a first logic gate configured to process the first mode signal and the second mode signal to produce a concurrent mode signal, wherein the array of memory cells, the redundancy enable circuit, and the error detection circuit are each further configured to be simultaneously active responsive to an assertion of the concurrent mode signal.
2 more elements
A method for a concurrent mode of operation for a memory, comprising:
- asserting a concurrent mode signal responsive to a simultaneous assertion of a first mode signal and a second mode signal to begin a concurrent mode of operation;
- during the concurrent mode of operation, activating an error detection circuit to compare a test vector read from an array of memory cells to a recorded test vector to identify a faulty feature in the array of memory cells and simultaneously activating a redundancy enable circuit to replace the faulty feature with a redundant feature;
- asserting the first mode signal while de-asserting the second mode signal to begin a diagnostic mode of operation;
- and
- activating the error detection circuit while the redundancy enable circuit is inactive during the diagnostic mode of operation.
2 more elements
A concurrent memory, comprising:
- a memory array;
- an error detection circuit configured to identify a faulty feature responsive to an assertion of a first mode signal;
- and
- a redundancy enable circuit configured to replace the faulty feature with a replacement feature responsive to an assertion of a second mode signal.
1 more element
Dependencies are inferred from the claim text.