Error detection and correction in memory
AssigneeMicron Technology, Inc.
InventorsJoseph M. McCrate, Robert J. Gleixner
Life of this patent
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Abstract
The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
Claims23
An apparatus, comprising:
- a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code;
- and
- circuitry configured to:
- perform a sense operation on the group of self-selecting memory cells by activating a sense amplifier with a check signal to detect a snapback of the self-selecting memory cells of the group;
- identify, based on the sense operation, memory cells of the group that cannot store data;
- mark data sensed from the identified memory cells as erasures;
- and
- perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
A method of operating memory, comprising:
- performing a first sense operation on a group of self-selecting memory cells comprising a word to sense data from the group of self-selecting memory cells;
- performing a second sense operation on the group of self-selecting memory cells after the first sense operation to identify memory cells of the group that cannot store data;
- marking bits in the word corresponding to the identified memory cells of the group as erasures;
- and
- performing an error correction operation on the data sensed from the group of self-selecting memory cells using a location of the bits in the word marked as erasures.
An apparatus comprising:
- a memory having a group of self-selecting memory cells;
- and
- circuitry configured to:
- perform a sense operation on the group of self-selecting memory cells to:
- sense data from the group of self-selecting memory cells;
- and
- identify memory cells of the group that cannot store data based on binary data from a check status latch;
- mark the data sensed from the identified memory cells of the group as erasures;
- and
- perform an error correction operation on the data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells of the group marked as erasures.
A method of operating memory, comprising:
- performing a bipolar sense operation on a group of self-selecting memory cells to identify memory cells of the group that cannot store data;
- marking data sensed from the identified memory cells of the group as erasures;
- and
- performing an error correction operation on the data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
Dependencies are inferred from the claim text.