Multiported parity scoreboard circuit

A method, comprising:

• reading a first bit of a first random-access memory circuit at an index corresponding to a first item,
• reading a second bit of a second random-access memory circuit at the index,
• determining the first item is busy in response to the exclusive-or function of the first bit and the second bit, and
• in response to a beginning of a first operation corresponding to the first item, reading a first value of the first bit, and writing to the first random-access memory circuit, at the index, the Boolean negation of the read first value of the first bit, and
• in response to the first operation or another operation completing, reading a first value of the second bit, and writing to the second random-access memory circuit, at the index, the Boolean negation of the read first value of the second bit.

An integrated circuit, comprising:

• a processor circuit including registers;
• and
• a scoreboard circuit, including:
• a first random-access memory circuit configured to store a respective first bit for each of the registers and to invert the respective first bit in response to a commencement of an operation corresponding to a respective one of the registers,
• a second random-access memory circuit configured to store a respective second bit for each of the registers and to invert the respective second bit in response to a completion of the operation;
• and
• a first-state-determining circuit configured to determine a state of a first one of the registers in response to the exclusive-or function of the first and second bits for the first one of the registers.

A non-transitory machine readable medium storing configuration data that when loaded into a field-programmable gate array, causes the field-programmable gate array to instantiate:

• an integrated circuit, comprising a processor circuit including registers and a including a scoreboard circuit, including
• a first random-access memory circuit configured to store a respective first bit for each of the registers and to invert the respective first bit in response to an operation corresponding to a respective one of the registers commencing;
• a second memory circuit configured to store a respective second bit for each of the registers and to invert the respective second bit in response to the operation completing;
• and
• a first state-determining circuit configured to determine a state of a first one of the registers in response to the exclusive-or function of the first and second bits for the first one of the registers.

A design tool that generates, configures, or incorporates a design file or a design library to configure an integrated circuit comprising:

• a processor circuit including registers;
• and
• a scoreboard circuit including
• a first random-access memory circuit configured to store a respective first bit for each of the registers and to invert the respective first bit in response to commencing an operation corresponding to a respective one of the registers,
• a second memory circuit configured to store a respective second bit for each of the registers and to invert the respective second bit in response to the operation completing, and
• first state-determining circuit configured to determine a state of a first one of the registers in response to the exclusive-or function of the first and second bits for the first one of the registers.

A scoreboard circuit, comprising:

• a first random-access memory circuit configured to store a first bit for a first item and to invert the first bit in response to a beginning of an operation corresponding to the first item;
• a second random-access memory circuit configured to store a second bit for the first item and to invert the second bit in response to the operation completing;
• and
• a state-determining circuit configured to determine a state of the first item in response to the exclusive-nor function of the first and second bits of the first item, read from the first and second random-access memory circuits, respectively.