Generating tie code fragments for binary translation

A system, comprising:

• a memory;
• and
• a processor coupled to the memory, wherein the processor is configured to:
• decode a first source code fragment compatible with a source instruction set architecture (ISA);
• translate, using a register mapping table, the first source code fragment into a first target code fragment compatible with a target ISA, wherein the register mapping table comprises a plurality of register mapping entries, each register mapping entry specifying a source register and a target register;
• decode a second source code fragment compatible with the source ISA;
• modify, based on decoding the second source code fragment, at least one register mapping entry of the register mapping table;
• translate, using the register mapping table, the second source code fragment into a second target code fragment compatible with the target ISA;
• and
• generate, based on the modified register mapping entry, a tie code fragment for connecting the first target code fragment and the second target code fragment;
• wherein
• each register mapping entry of the register mapping table further comprises a weight value which is proportional to a usage frequency of a corresponding target register multiplied by a latest value of a usage path length of the corresponding target register.

A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a computer system, cause the computer system to:

• decoding, by a computer system, a first source code fragment compatible with a source instruction set architecture (ISA);
• translating, using a register mapping table, the first source code fragment into a first target code fragment compatible with a target ISA, wherein the register mapping table comprises a plurality of register mapping entries, each register mapping entry specifying a source register and a target register;
• decoding a second source code fragment compatible with the source ISA;
• modifying, based on decoding the second source code fragment, at least one register mapping entry of the register mapping table;
• translating, using the register mapping table, the second source code fragment into a second target code fragment compatible with the target ISA;
• and
• generating, based on the modified register mapping entry, a tie code fragment for connecting the first target code fragment and the second target code fragment;
• wherein
• each register mapping entry of the register mapping table further comprises a weight value which is proportional to a usage frequency of a corresponding target register multiplied by a latest value of a usage path length of the corresponding target register.

A method comprising:

• decoding, by a computer system, a first source code fragment compatible with a source instruction set architecture (ISA);
• translating, using a register mapping table, the first source code fragment into a first target code fragment compatible with a target ISA, wherein the register mapping table comprises a plurality of register mapping entries, each register mapping entry specifying a source register and a target register representing the source register in the first target code fragment;
• decoding a second source code fragment compatible with the source ISA;
• modifying, based on decoding the second source code fragment, at least one register mapping entry of the register mapping table;
• translating, using the register mapping table, the second source code fragment into a second target code fragment compatible with the target ISA;
• generating, based on the modified register mapping entry, a tie code fragment for connecting the first target code fragment and the second target code fragment;
• and
• iteratively processing the first source code fragment and the second source code fragment until the tie code fragment is stabilized.

A method comprising:

• decoding, by a computer system, a first source code fragment compatible with a source instruction set architecture (ISA);
• translating, using a register mapping table, the first source code fragment into a first target code fragment compatible with a target ISA, wherein the register mapping table comprises a plurality of register mapping entries, each register mapping entry specifying a source register and a target register representing the source register in the first target code fragment;
• decoding a second source code fragment compatible with the source ISA;
• modifying, based on decoding the second source code fragment, at least one register mapping entry of the register mapping table;
• translating, using the register mapping table, the second source code fragment into a second target code fragment compatible with the target ISA;
• and
• generating, based on the modified register mapping entry, a tie code fragment for connecting the first target code fragment and the second target code fragment;
• wherein
• modifying the register mapping entry further comprises:
• identifying a first source register referenced by the first source code fragment;
• identifying, among the plurality of mapping table entries, a mapping table entry comprising a highest weight value, wherein the identified mapping table entry specifies a second source register and a second target register;
• and
• replacing, in the identified mapping table entry, an identifier of the second source register with an identifier of the first source register replacing, in the identified mapping table entry, an identifier of the second source register with an identifier of the first source register;
• wherein
• the weight value is at least one of indicative of a number of binary translation iterations that were performed after a corresponding target register was utilized and indicative of a usage frequency of a corresponding target register.

A method comprising:

• decoding, by a computer system, a first source code fragment compatible with a source instruction set architecture (ISA);
• translating, using a register mapping table, the first source code fragment into a first target code fragment compatible with a target ISA, wherein the register mapping table comprises a plurality of register mapping entries, each register mapping entry specifying a source register and a target register representing the source register in the first target code fragment;
• decoding a second source code fragment compatible with the source ISA;
• modifying, based on decoding the second source code fragment, at least one register mapping entry of the register mapping table;
• translating, using the register mapping table, the second source code fragment into a second target code fragment compatible with the target ISA;
• generating, based on the modified register mapping entry, a tie code fragment for connecting the first target code fragment and the second target code fragment;
• and
• iteratively processing the first source code fragment and the second source code fragment until the tie code fragment is stabilized;
• wherein
• each register mapping entry of the register mapping table further comprises a weight value indicative of a number of binary translation iterations that were performed until the tie code fragment was stabilized.

A method comprising:

• decoding, by a computer system, a first source code fragment compatible with a source instruction set architecture (ISA);
• translating, using a register mapping table, the first source code fragment into a first target code fragment compatible with a target ISA, wherein the register mapping table comprises a plurality of register mapping entries, each register mapping entry specifying a source register and a target register representing the source register in the first target code fragment;
• decoding a second source code fragment compatible with the source ISA;
• modifying, based on decoding the second source code fragment, at least one register mapping entry of the register mapping table;
• translating, using the register mapping table, the second source code fragment into a second target code fragment compatible with the target ISA;
• and
• generating, based on the modified register mapping entry, a tie code fragment for connecting the first target code fragment and the second target code fragment;
• wherein each register mapping entry of the register mapping table further comprises a weight value;
• and
• one of:
• the weight value is proportional to a ratio of a number of times a target register has been used to the total number of code fragments generated for a given binary code module performing binary code translations;
• and
• the weight value is proportional to a target register usage frequency multiplied by a latest value of a usage path length of the target register usage and the usage path length is established in dependence upon a number of sequentially executed target code fragments which utilize the same assignment of the target register.