Ultra-low precision floating-point fused multiply-accumulate unit

A system for implementing a fused multiply-multiply-accumulate (FMMA) operation in a computing environment, comprising:

• one or more hardware memory storing executable instructions;
• one or more hardware processors;
• and
• a FMMA unit implemented within the one or more hardware processors, wherein the one or more hardware processors are configured to:
• receive, by the one or more hardware processors, one of the executable instructions stored in the one or more memory, wherein the instruction contains at least two operands of mixed bit-precision formats;
• and
• execute the one of the executable instructions by implementing the FMMA unit to perform an internal rounding operation associated with floating point arithmetic performing each of:
• determining by multiplier circuitry within the FMMA unit, in parallel, mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two products having a larger exponent, wherein the mantissas are pre-shifted prior to aligning the addend and the product relative to the alternative product, and wherein the addend and the product having the smallest exponent are aligned prior to receiving a select signal indicating to a selector to select between one of the pre-shifted mantissas when performing the alignment of the addend and the product relative to the alternative product;
• aligning, by aligning circuitry within the FMMA unit, the addend relative to the alternative product having the larger exponent;
• and
• aligning, by the aligning circuitry, the product having the smallest exponent relative to the alternative product having the larger exponent according to the alignment shift amount for the product of the two products having the smallest exponent.

A computer program product for, by a processor, implementing a fused multiply-multiply-accumulate (FMMA) operation in a computing environment, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:

• an executable portion that receives, by the processor, an instruction stored in a memory, wherein the instruction contains at least two operands of mixed bit-precision formats;
• and
• an executable portion that executes the instruction, wherein, when executing the instruction, the one or more processors implement a FMMA unit to perform an internal rounding operation associated with floating point arithmetic of the instruction by performing each of:
• determining, in parallel, mantissas for two products, an exponent difference of the two products serving as an alignment shift amount for a product of the two products having a smallest exponent, and an alignment shift amount for an addend relative to an alternative product of the two products having a larger exponent, wherein the mantissas are pre-shifted prior to aligning the addend and the product relative to the alternative product, and wherein the addend and the product having the smallest exponent are aligned prior to receiving a select signal indicating to a selector to select between one of the pre-shifted mantissas when performing the alignment of the addend and the product relative to the alternative product;
• aligning, by aligning circuitry within the FMMA unit, the addend relative to the alternative product having the larger exponent;
• and
• aligning, by the aligning circuitry, the product having the smallest exponent relative to the alternative product having the larger exponent according to the alignment shift amount for the product of the two products having the smallest exponent.