Using dynamic bursts to support frequency-agile memory interfaces
AssigneeRambus Inc.
InventorsJared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
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Abstract
The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
Claims20
A method, comprising:
- responsive to a change in an instantaneous data rate of a first interface from a data rate R1 to a relatively slower data rate R2, decreasing an average data rate of a second interface by substantially R2/R1.
An integrated circuit, comprising:
- a first interface to operate at an instantaneous data rate R1 or a relatively slower instantaneous data rate R2;
- a second interface;
- and
- circuitry to decrease an average data rate of the second interface by substantially R2/R1 upon detecting that the instantaneous data rate of the first interface changed from R1 to R2.
An integrated circuit, comprising:
- a first interface;
- a second interface;
- first circuitry to detect whether a reference clock signal received on the first interface is operating at a full rate or one of a plurality of subrates, each subrate having a corresponding burst mode with a low-power interval setting specific to that burst mode;
- and
- second circuitry to decrease an average data rate of the second interface in response to detecting that the reference clock signal changed from the full rate to one of the plurality of subrates.
Dependencies are inferred from the claim text.