Array substrate, manufacturing method thereof, and display panel

A method of manufacturing an array substrate, comprising:

• forming a driving circuit layer on a substrate;
• forming a first insulating layer on the driving circuit layer;
• forming a first via hole on the first insulating layer to expose a first portion of the driving circuit layer;
• forming a pixel electrode layer on the first insulating layer, so that the pixel electrode layer is electrically connected to the driving circuit layer through the first via hole;
• and
• forming a second via hole in the pixel electrode layer corresponding to the first via hole, to expose a second portion of the pixel electrode layer;
• wherein the driving circuit layer comprises a gate layer and a source/drain layer, the gate layer comprises a plurality of scan lines and a gate, and the source/drain layer comprises a source/drain and a plurality of data lines disposed perpendicular to the scan lines;
• and
• wherein the array substrate further comprises a plurality of volatilization via holes close to the first via hole, the volatilization via holes penetrate the pixel electrode layer and the first insulating layer, and expose part of the source/drain.

A display panel, comprising an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate comprises:

• a substrate, a driving circuit layer located on the substrate, and a pixel electrode layer located on the driving circuit layer, wherein the pixel electrode layer is electrically connected to the driving circuit layer through a first via hole;
• and
• wherein the pixel electrode layer further comprises at least one second via hole located in the first via hole, and the second via hole exposes a part of the driving circuit layer;
• wherein the driving circuit layer comprises a gate layer and a source/drain layer, the gate layer comprises a plurality of scan lines and a gate, and the source/drain layer comprises a source/drain and a plurality of data lines disposed perpendicular to the scan lines;
• and
• wherein the array substrate further comprises a plurality of volatilization via holes close to the first via hole, the volatilization via holes penetrate the pixel electrode layer and the first insulating layer, and expose part of the source/drain.