Integrated circuit spike check test point identification apparatus and method

A nontransitory computer-readable program storage medium having stored thereon program instructions that when executed by a processor have the processor capable of:

• receiving a set of input data, the input data comprising test board attributes, the attributes comprising identification of devices coupled to the test board, the test board further comprising a plurality of conductive surfaces, each conductive surface in the plurality of conductive surfaces for electrical communication with a respective pin of a plurality of pins of a device under test;
• transforming the set of input data into test board mapping data, the test board mapping data comprising, for each conductive surface for electrical communication with a respective pin of the plurality of pins, an ordered listing of potential test points along a path that couples to the conductive surface, wherein the potential test points are derived from at least one of the test board attributes;
• identifying, for each of the conductive surfaces coupled for electrical communication with a respective pin of the plurality of pins, a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test
• wherein the transforming transforms the set of input data into test board mapping data comprising whether a path comprises a relay with an associated relay control bit;
• and
• wherein the identifying comprises excluding identification of the relay control bit as the selected test point.

A nontransitory computer-readable program storage medium having stored thereon program instructions that when executed by a processor have the processor capable of:

• receiving a set of input data, the input data comprising test board attributes, the attributes comprising identification of devices coupled to the test board, the test board further comprising a plurality of conductive surfaces, each conductive surface in the plurality of conductive surfaces for electrical communication with a respective pin of a plurality of pins of a device under test;
• transforming the set of input data into test board mapping data, the test board mapping data comprising, for each conductive surface for electrical communication with a respective pin of the plurality of pins, an ordered listing of potential test points along a path that couples to the conductive surface, wherein the potential test points are derived from at least one of the test board attributes;
• identifying, for each of the conductive surfaces coupled for electrical communication with a respective pin of the plurality of pins, a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test
• wherein the transforming transforms the set of input data into test board mapping data comprising whether a device is a shared instrument on the test board for concurrently testing multiple devices under test;
• and
• wherein the identifying comprises excluding identification of the shared instrument as the selected test point.

A nontransitory computer-readable program storage medium having stored thereon program instructions that when executed by a processor have the processor capable of:

• receiving a set of input data, the input data comprising test board attributes, the attributes comprising identification of devices coupled to the test board, the test board further comprising a plurality of conductive surfaces, each conductive surface in the plurality of conductive surfaces for electrical communication with a respective pin of a plurality of pins of a device under test;
• transforming the set of input data into test board mapping data, the test board mapping data comprising, for each conductive surface for electrical communication with a respective pin of the plurality of pins, an ordered listing of potential test points along a path that couples to the conductive surface, wherein the potential test points are derived from at least one of the test board attributes;
• and
• identifying, for each of the conductive surfaces coupled for electrical communication with a respective pin of the plurality of pins, a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test
• wherein the identification of devices comprises identification of an integrated circuit;
• and
• wherein the transforming comprises a transform of the identification of the integrated circuit into an ordered listing of potential test points from a first pin of the integrated circuit to a second pin of the integrated circuit.

A method of operating a system comprising a processor, the method comprising:

• receiving a set of input data, the input data comprising test board attributes, the attributes comprising identification of devices coupled to the test board, the test board further comprising a plurality of conductive surfaces, each conductive surface in the plurality of conductive surfaces for electrical communication with a respective pin of a plurality of pins of a device under test;
• transforming the set of input data into test board mapping data, the test board mapping data comprising, for each conductive surface for electrical communication with a respective pin of the plurality of pins, an ordered listing of potential test points along a path that couples to the conductive surface, wherein the potential test points are derived from at least one of the test board attributes;
• and
• identifying, for each of the conductive surfaces coupled for electrical communication with a respective pin of the plurality of pins, a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test.

A method of operating a system comprising a processor, the method comprising:

• receiving a set of input data, the input data comprising test board attributes, the attributes comprising identification of devices coupled to the test board, the test board further comprising a plurality of conductive surfaces, each conductive surface in the plurality of conductive surfaces for electrical communication with a respective pin of a plurality of pins of a device under test;
• transforming the set of input data into test board mapping data, the test board mapping data comprising, for each conductive surface for electrical communication with a respective pin of the plurality of pins, an ordered listing of potential test points along a path that couples to the conductive surface, wherein the potential test points are derived from at least one of the test board attributes;
• and
• identifying, for each of the conductive surfaces coupled for electrical communication with a respective pin of the plurality of pins, a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test
• wherein the identifying comprises identifying an integrated circuit;
• and
• wherein the transforming comprises transforming the identification of the integrated circuit into an ordered listing of potential test points from a first pin of the integrated circuit to a second pin of the integrated circuit.