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US 11,453,212 B2Granted
Print component with memory circuit
AssigneeHewlett-Packard Development Company, L.P.
InventorsBoon Bing Ng, James Michael Gardner
Life of this patent
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Abstract
A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signals paths which communicate operating signals to the print component, and a memory component to store memory values associated with the print component. A control circuit to, in response to identifying a sequence of operating signals representing a memory read, provide a first analog signal on the analog pad in parallel with a second analog signal from the print component to provide an analog electrical value on the analog pad representing stored memory values selected by the memory read.
Claims22
A memory circuit for a print component comprising:
- a plurality of I/O pads, including an analog pad, to connect to a plurality of signals paths which communicate operating signals to the print component;
- a memory component to store memory values associated with the print component;
- and
- a control circuit, in response to identifying a sequence of operating signals representing a memory read of selected stored memory values, the control circuit to provide a first analog signal on the analog pad, the first analog signal to combine with a second analog signal on the analog pad from the print component to provide an analog electrical value on the analog pad representing stored memory values selected by the memory read.
1 more element
A print component comprising:
- a plurality of I/O pads, including an analog pad, to communicate operating signals for operating the print component;
- a fluidic ejection circuit coupled to the I/O pads including:
- an array of fluid actuators;
- and
- an array of memory elements, each memory element to store a data bit having a bit value representing information associated with the print component;
- and
- a memory circuit including:
- a memory component to store memory values associated with the print component, each memory value of at least a portion of the memory values of the memory component corresponding to a different one of the memory elements, where the memory value may be different than the bit value of the corresponding memory element;
- and
- a control circuit to, in response to identifying a sequence of operating signals representing a memory read of selected memory elements, provide a first analog signal on the analog pad in parallel with a second analog signal from the fluid ejection circuit representing bit values of the selected memory elements to provide an analog electrical value on the analog pad representing stored memory values corresponding to the selected memory elements, the control circuit to adjust the first analog signal such that the first analog signal and the second analog signal together result in the analog electrical value on the analog pad representing an expected analog electrical value corresponding to the stored memory values corresponding to the selected memory elements of the print component.
7 more elements
A print component comprising:
- a plurality of fluidic ejection die, each including:
- an array of fluid actuators;
- and
- an array of memory elements, each memory element to store a data bit having a bit value;
- a plurality of I/O pads communicating operating signals for operating the print component, including a separate data pad for each fluidic ejection circuit and an analog pad shared by each fluidic ejection circuit;
- and
- a memory die coupled to the I/O pads in parallel with each fluidic ejection die, the memory die including:
- a memory component to store memory values, each memory value corresponding to a different one of the memory elements of the plurality of fluidic ejection die, where the memory value may be different from the bit value of the corresponding memory element;
- and
- a control circuit, in response to a sequence of operating signals representing a memory read of selected memory elements of the plurality of fluidic die, the control circuit to provide a first analog signal on the analog pad to combine with a second analog signal on the analog pad from the fluidic ejection die representing the bit values of the selected memory elements so that a resulting analog electrical value from the combined first and second analog signals on the analog pad represents the stored memory values corresponding to the selected memory elements.
7 more elements
Dependencies are inferred from the claim text.