# US 11,451,734 B2 · Image sensor for supporting plural capturing modes > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,451,734 B2 - Document ID: US11451734B2 - Status: Granted - Kind: B2 - Application number: 16/898,018 - Filed: 2020-06-10 - Published: 2021-04-22 - Granted: 2022-09-20 - Earliest claimed: 2019-10-22 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Junghyun Kim - Web page: https://patentgrep.com/patent/US11451734B2 ## CPC - H04N 25/766: comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power - H04N 25/702: SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H10F 39/151: {Geometry or disposition of pixel elements, address lines or gate electrodes} - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/8023: {Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery} - H10F 39/8027: {Geometry of the photosensitive area} - H10F 39/8063: {Microlenses} - H10F 39/807: {Pixel isolation structures} - H10F 39/8037: {the integrated elements comprising a transistor} - H10F 39/813: {Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels} - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract An image sensor includes a pixel array including a central region in which plural first pixels output first pixel information and a peripheral region in which plural second pixels output second pixel information, the peripheral region surrounding the central region. A size of a second pixel, of the plural second pixels, is 4n times greater than that of a first pixel, of the plural first pixels, n being an integer. ## Claims ### Claim 1 An image sensor comprising a pixel array including a central region in which plural first pixels output first pixel information and a peripheral region in which plural second pixels output second pixel information, the peripheral region surrounding the central region, wherein a size of a second pixel, of the plural second pixels, is 4n times greater than that of a first pixel, of the plural first pixels, n being an integer, wherein the first pixel information is transferred via a single column line coupling the first pixel of the pixel array to signal output circuitry, and the second pixel information is transferred via one of plural column lines each coupling the second pixel of the pixel array to the signal output circuitry. ### Claim 2 (depends on 1) The image sensor according to claim 1, wherein the first pixel comprises a single photodiode and a single lens over the single photodiode, and the second pixel comprises plural photodiodes and a single lens over the plural photodiodes. ### Claim 3 (depends on 1) The image sensor according to claim 1, wherein the second pixel comprises: plural transfer gates, each configured to couple a respective one of the plural photodiodes to a floating diffusion area; plural reset gates configured to reset the floating diffusion area; and plural select gates, each configured to be turned on in response to an amount of charge accumulated in the floating diffusion area, wherein only one of the plural select gates is turned on. ### Claim 4 (depends on 1) The image sensor according to claim 1, wherein each of the first pixel and the second pixel individually comprise a single photodiode and a single lens over the single photodiode. ### Claim 5 An image sensor, comprising: a pixel array including a central region in which plural first pixels each output first pixel information and a peripheral region in which plural second pixels each output second pixel information, the peripheral region surrounding the central region; and signal output circuitry configured to combine first pixel information, individually outputted from each pixel in a set of adjacent pixels, among the plural first pixels, to generate third pixel information for output in a first operation mode, wherein the first pixel information is transferred via a single column line coupling the first pixel of the pixel array to signal output circuitry, and the second pixel information is transferred via one of plural column lines each coupling the second pixel of the pixel array to the signal output circuitry. ### Claim 6 (depends on 5) The image sensor according to claim 5, wherein the signal output circuitry is configured to output the first pixel information outputted from the plural first pixels of the central region in a second operation mode which is distinguishable from the first operation mode, and wherein the signal output circuitry is configured to screen the second pixel information outputted from the plural second pixels of the peripheral region in the second operation mode. ### Claim 7 (depends on 5) The image sensor according to claim 5, wherein the number of pixels in the set of adjacent pixels which output first pixel information that is combined by the signal output circuitry is determined based on a ratio of a flat size of the first pixel to a flat size of the second pixel. ### Claim 8 (depends on 7) The image sensor according to claim 7, wherein the flat size of the first pixel is ¼n times of the flat size of the second pixel, where n is an integer of 1 or greater. ### Claim 9 (depends on 7) The image sensor according to claim 7, wherein the signal output circuitry is configured to: receive an operation mode signal and a row address of the pixel array; and determine, based on the operation mode signal and the row address, which of the first and second pixels pixel information is transferred via a column line when the column line crosses the first and second regions. ### Claim 10 An image sensor, comprising: a pixel array including a first region including plural first pixels, each having a first planar area, and a second region including plural second pixels, each having a second planar area; and signal output circuitry configured, based on an operation mode, to output either first pixel information outputted from each of the plural first pixels or third pixel information obtained and combined from the plural first pixels, wherein the first pixel information corresponds to a size of the first planar area and the third pixel information corresponds to a size of the second planar area, and wherein the first pixel information is transferred via a single column line coupling the first pixel of the pixel array to the signal output circuitry, and second pixel information is transferred via one of plural column lines each coupling the second pixel of the pixel array to the signal output circuitry. ### Claim 11 (depends on 10) The image sensor according to claim 10, wherein the signal output circuitry is configured, in a first operation mode, to output the third pixel information, and wherein the signal output circuitry is configured, in the first operation mode, to output second pixel information obtained from the plural second pixels in the second region. ### Claim 12 (depends on 11) The image sensor according to claim 11, wherein the signal output circuitry is configured, in a second operation mode, to output the first pixel information, and wherein the signal output circuitry is configured, in the second operation mode, to screen the second pixel information. ### Claim 13 (depends on 10) The image sensor according to claim 10, wherein the pixel array further comprises a third region including plural third pixels, each having a third planar area, wherein the signal output circuitry is configured, based on the operation mode, to output one among the first pixel information, the third pixel information and fifth pixel information obtained from the plural first pixels, wherein the signal output circuitry is configured to generate the fifth pixel information by combining some of the first pixel information, wherein the fifth pixel information corresponds to the third planar area, wherein the signal output circuitry is further configured, based on the operation mode, to output either second pixel information outputted from each of the plural second pixels and fourth pixel information respectively obtained and combined from the plural second pixels, and wherein the fourth pixel information corresponds to a size of the third planar area. ### Claim 14 (depends on 13) The image sensor according to claim 13, wherein the third planar area is larger than the second planar area, and the second planar area is larger than the first planar area. ### Claim 15 (depends on 13) The image sensor according to claim 13, wherein the signal output circuitry is configured, in a first operation mode, to output the fifth pixel information and the fourth pixel information, and wherein the signal output circuitry is configured, in the first operation mode, to output sixth pixel information obtained from the plural third pixels in the third region. ### Claim 16 (depends on 13) The image sensor according to claim 13, wherein the signal output circuitry is configured, in a second operation mode, to output the third pixel information and the second pixel information, and wherein the signal output circuitry is configured, in the second operation mode, to screen sixth pixel information obtained from the plural third pixels in the third region. ### Claim 17 (depends on 13) The image sensor according to claim 13, wherein the signal output circuitry is configured, in a third operation mode, to output the first pixel information, and wherein the signal output circuitry is configured, in the third operation mode, to output to screen both the second pixel information and sixth pixel information obtained from the plural third pixels in the third region. ### Claim 18 (depends on 10) The image sensor according to claim 10, wherein the signal output circuitry is configured to: receive an operation mode signal and a row address of the pixel array, determine, based on the operation mode signal and the row address, which of the first to third pixels pixel information is transferred via a column line when the column line crosses the first to third regions, and determine, based on the operation mode signal and the row address, which of the second and third pixels pixel information is transferred via another column line when the another column line crosses the second and third regions.