# US 11,451,731 B2 · Counter circuit and image sensor including the same

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- Number: US 11,451,731 B2
- Document ID: US11451731B2
- Status: Granted
- Kind: B2
- Application number: 16/908,980
- Filed: 2020-06-23
- Published: 2021-04-22
- Granted: 2022-09-20
- Earliest claimed: 2019-10-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jahyun Koo; Hyeokjong Lee
- Web page: https://patentgrep.com/patent/US11451731B2

## CPC

- H03M 1/1295: {Clamping, i.e. adjusting the DC level of the input signal to a predetermined value}
- H03M 1/162: {the steps being performed sequentially in a single stage, i.e. recirculation type (H03M1/161 takes precedence)}
- H04N 25/46: by combining or binning pixels
- H04N 25/616: involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
- H04N 25/618: for random or high-frequency noise
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements}
- H03M 1/123: {Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters}
- H03M 1/56: Input signal compared with linear ramp
- H04N 25/7795: {Circuitry for generating timing or clock signals}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

An image sensor includes a pixel sensor outputting an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal that is time-axis length information; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.

## Claims

### Claim 1

An image sensor, comprising:
a pixel sensor configured to sense an incident light and to output an analog sampling signal;
a sampling unit configured to compare the sampling signal and a ramp signal, and to output a comparison signal that is time-axis length information; and
a counter configured to count a length of the comparison signal in response to a clock signal, a first complement control signal, and a second complement control signal, wherein:
the counter includes:
a first AND gate configured to perform an AND operation on the comparison signal and the clock signal; and
a first counting unit triggered at a falling edge of an output of the first AND gate to output a first count value, and
the first counting unit includes:
a first complement operation controller configured to store an inverted first count value corresponding to an inverted version of the first count value in response to the first complement control signal, and to output the inverted first count value in response to the second complement control signal; and
a first D-flip-flop that is set or reset depending on the inverted first count value output from the first complement operation controller, and configured to output the first count value.

### Claim 2 (depends on 1)

The image sensor of claim 1, wherein the first complement operation controller includes:
a D-latch configured to store the inverted first count value in response to the first complement control signal; and
a logic gate configured to transfer the inverted first count value stored in the D-latch to the first D-flip-flop in response to the second complement control signal.

### Claim 3 (depends on 2)

The image sensor of claim 2, wherein the logic gate includes:
a second AND gate configured to perform a first AND operation on a non-inverted output signal of the D-latch and the second complement control signal, and to transfer a result of the first AND operation to a set input terminal of the D-flip-flop; and
a third AND gate configured to perform a second AND operation on an inverted output signal of the D-latch and the second complement control signal, and to transfer a result of the second AND operation to a reset input terminal of the D-flip-flop.

### Claim 4 (depends on 3)

The image sensor of claim 3, wherein, as the inverted first count value, an inverted output signal of the first D-flip-flop is fed back to a data input terminal of the first D-flip-flop.

### Claim 5 (depends on 2)

The image sensor of claim 2, wherein the D-latch stores the inverted first count value in response to a falling edge of the first complement control signal.

### Claim 6 (depends on 1)

The image sensor of claim 1, wherein the counter further includes a second counting unit that is triggered at a falling edge of the first count value to output a second count value being an upper bit of the first count value, the second counting unit including:
a second complement operation controller configured to store an inverted second count value that is an inverted version of the second count value in response to the first complement control signal, and to output the inverted second count value in response to the second complement control signal; and
a second D-flip-flop that is set or reset depending on the inverted second count value output from the second complement operation controller, and configured to output the second count value at a falling edge of the first count value.

### Claim 7 (depends on 6)

The image sensor of claim 6, wherein the first counting unit further includes a first multiplexer configured to select, in response to a division control signal, one of the inverted first count value and the inverted second count value to be transferred to the first complement operation controller.

### Claim 8 (depends on 7)

The image sensor of claim 7, wherein, when the division control signal and the first and second complement control signals are activated, the first counting unit stores and outputs the inverted second count value.

### Claim 9

A counter circuit that counts a high period or a low period of an input signal using a clock signal, the counter circuit comprising:
a first AND gate configured to perform an AND operation on the input signal and the clock signal; and
a ripple counter triggered by an output of the first AND gate to count a length of the input signal, the ripple counter including a plurality of counting units for counting up or counting down the length of the input signal, each of the plurality of counting units including:
a D-latch configured to store an inverted counting bit in response to a first complement control signal; and
a D-flip-flop that is set or reset by the inverted counting bit stored in the D-latch in response to a second complement control signal.

### Claim 10 (depends on 9)

The counter circuit of claim 9, wherein each of the plurality of counting units further includes:
a second AND gate configured to transfer a non-inverted output signal of the D-latch to a set input terminal of the D-flip-flop in synchronization with the second complement control signal; and
a third AND gate configured to transfer an inverted output signal of the D-latch to a reset input terminal of the D-flip-flop in synchronization with the second complement control signal.

### Claim 11 (depends on 10)

The counter circuit of claim 10, wherein the ripple counter includes:
a first counting unit configured to toggle a least significant count value in synchronization with a falling edge of an output of the first AND gate; and
a second counting unit triggered at a falling edge of an output of the first counting unit.

### Claim 12 (depends on 11)

The counter circuit of claim 11, wherein an inverted output terminal of the first counting unit is connected to a data input terminal of the first counting unit.

### Claim 13 (depends on 9)

The counter circuit of claim 9, wherein the first complement control signal and the second complement control signal sequentially transition to a high level to generate a complement of current count bits of the ripple counter.

### Claim 14

A counter circuit that counts a high period or a low period of an input signal using a clock signal, the counter circuit comprising:
a first AND gate configured to perform an AND operation on the input signal and the clock signal; and
a ripple counter including a first counting unit and a second counting unit that are triggered by an output of the first AND gate to count a length of the input signal, the first counting unit toggling a first count bit, and the second counting unit toggling a second count bit that is an upper bit of the first count bit,
wherein, when a division control signal is activated, the first counting unit latches and outputs an inverted second count bit that is an inverted version of the second count bit toggled by the second counting unit.

### Claim 15 (depends on 14)

The counter circuit of claim 14, wherein the first counting unit includes:
a multiplexer configured to select one of an inverted first count bit, which is an inverted version of the first count bit, and the inverted second count bit depending on the division control signal;
a complement operation controller configured to latch an output of the multiplexer in response to a first complement control signal, and to output the latched output in response to a second complement control signal; and
a D-flip-flop that is set or reset depending on the latched output stored in the complement operation controller.

### Claim 16 (depends on 15)

The counter circuit of claim 15, wherein, when the division control signal is activated, the multiplexer selects the inverted second count bit to be provided to the complement operation controller.

### Claim 17 (depends on 16)

The counter circuit of claim 16, wherein the complement operation controller further includes:
a D-latch configured to store the output of the multiplexer in response to the first complement control signal;
a second AND gate configured to transfer a non-inverted output signal of the D-latch to a set input terminal of the D-flip-flop in synchronization with the second complement control signal; and
a third AND gate configured to transfer an inverted output signal of the D-latch to a reset input terminal of the D-flip-flop in synchronization with the second complement control signal.

### Claim 18 (depends on 17)

The counter circuit of claim 17, wherein an inverted output signal of the D-flip-flop is fed back as the inverted first count bit of the multiplexer.

### Claim 19 (depends on 17)

The counter circuit of claim 17, wherein, when the first complement control signal and the second complement control signal are sequentially activated in a state where the division control signal is activated, a complement operation and a division operation are continuously performed on a count value corresponding to the input signal.