# US 11,451,416 B2 · Signal equalizer and signal equalizing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,451,416 B2 - Document ID: US11451416B2 - Status: Granted - Kind: B2 - Application number: 16/987,378 - Filed: 2020-08-06 - Published: 2021-07-08 - Granted: 2022-09-20 - Earliest claimed: 2020-01-06 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corp. - Inventors: Yao-Chia Liu - Web page: https://patentgrep.com/patent/US11451416B2 ## CPC - H04L 25/03057: {with a recursive structure (H04L25/03031 takes precedence)} - H04L 25/03006: {Arrangements for removing intersymbol interference} - H04L 25/03828: {Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties (partial response systems H04L25/497)} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A signal equalizer comprising: a feedback system, configured to acquire at least one signal value of an edge region of an input signal, and configured to adjust the signal value according to a crossing part of an eye diagram such that the crossing part converges to a zero point, wherein the crossing part corresponds to the edge region. ## Claims ### Claim 1 A signal equalizer, comprising: a feedback system, configured to acquire at least one signal value of an edge region of an input signal, and configured to adjust the signal value according to a crossing part of an eye diagram such that the crossing part converges to a zero point, wherein the crossing part corresponds to the edge region. ### Claim 2 (depends on 1) The signal equalizer of claim 1, wherein the feedback system comprises a first feedback circuit comprising: a first sampling circuit, configured to acquire at least portion of the signal value by sampling a non-edge region of the input signal according to a first type of edge of a sampling clock signal; an adjust value determining circuit, configured to determine at least one first adjusting value according to the signal value and the crossing part; and an adjusting circuit, configured to adjust the edge region according to the first adjusting value, such that the crossing part converges to the zero point. ### Claim 3 (depends on 2) The signal equalizer of claim 2, wherein the first feedback circuit further comprises: a second sampling circuit, configured to acquire another portion of the signal value by sampling the edge region of the input signal according to a second type of edge of the sampling clock signal. ### Claim 4 (depends on 2) The signal equalizer of claim 2, wherein the feedback system comprises a second feedback circuit configured to adjust at least one signal part of the input signal, such that an eye diagram part corresponding to the signal part converges to an upper noise region average voltage and a lower noise region average voltage. ### Claim 5 (depends on 4) The signal equalizer of claim 4, wherein the signal part is a first signal value of the input signal, wherein the first signal value is a signal value first sampled by the sampling clock signal. ### Claim 6 (depends on 4) The signal equalizer of claim 4, wherein the signal part is a non-edge region of the input signal. ### Claim 7 (depends on 4) The signal equalizer of claim 4, wherein the signal part is a previous bit of the edge region. ### Claim 8 (depends on 4) The signal equalizer of claim 4, wherein the first feedback circuit comprises the first sampling circuit and a plurality of amplifiers; where the second feedback circuit generates a second adjusting value according to the upper noise region average voltage and the lower noise region average voltage; wherein the first sampling circuit comprises a plurality of sample and hold circuits coupled in series; and where one shared amplifier among the amplifies receives the second adjusting value and an output of a first one of the sample and hold circuits to adjust the signal part. ### Claim 9 (depends on 8) The signal equalizer of claim 8, comprising an adder, wherein the amplifiers output to the adder. ### Claim 10 (depends on 8) The signal equalizer of claim 8, comprising two adders; wherein the shared amplifier outputs to one of the adders, and the amplifier which is not the shared amplifier outputs to the other one of the adders. ### Claim 11 A signal equalizing method, comprising: acquiring at least one signal value of an edge region of an input signal; and adjusting the signal value according to a crossing part of an eye diagram such that the crossing part converges to a zero point, wherein the crossing part corresponds to the edge region. ### Claim 12 (depends on 11) The signal equalizing method of claim 11, comprising: acquiring at least portion of the signal value by sampling a non-edge region of the input signal according to a first type of edge of a sampling clock signal; determining at least one first adjusting value according to the signal value and the crossing part; and adjusting the edge region according to the first adjusting value, such that the crossing part converges to the zero point. ### Claim 13 (depends on 12) The signal equalizing method of claim 12, wherein the first adjusting value is a gain value, wherein the step of adjusting the signal value comprising using the gain value to amplify the signal value. ### Claim 14 (depends on 12) The signal equalizing method of claim 12, further comprising: acquiring another portion of the signal value by sampling the edge region of the input signal according to a second type of edge of the sampling clock signal. ### Claim 15 (depends on 14) The signal equalizing method of claim 14, wherein the first type of edge is a positive edge and the second type of edge is a negative edge. ### Claim 16 (depends on 12) The signal equalizing method of claim 12, further comprising: adjusting at least one signal part of the input signal, such that an eye diagram part corresponding to the signal part converges to an upper noise region average voltage and a lower noise region average voltage. ### Claim 17 (depends on 16) The signal equalizing method of claim 16, wherein the signal part is a first signal value of the input signal, wherein the first signal value is a signal value first sampled by the sampling clock signal. ### Claim 18 (depends on 16) The signal equalizing method of claim 16, wherein the signal part is the non-edge region of the input signal. ### Claim 19 (depends on 18) The signal equalizing method of claim 18, wherein the signal part is a previous bit of the edge region.