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US 11,451,415 B2Granted
Circuitry for increasing bandwidth and reducing interference in memory signals
AssigneeMicron Technology, Inc.
InventorsTaylor Loftsgaarden, Ming-ta Hsieh
Life of this patent
Estimating the term…
Abstract
Signals sent to a memory component are received by circuitry included in the memory component. The circuitry comprises a comparator circuit to process the received signals. The circuitry further comprises a resistor-capacitor (RC) circuit coupled to the comparator circuit to increase bandwidth and reduce interference in the received signals processed by the comparator circuit.
Claims17
A system, comprising:
- a memory component;
- and
- circuitry included in the memory component to receive signals sent to the memory component, wherein the circuitry comprises:
- a comparator circuit to process the received signals, wherein the comparator circuit includes:
- a first transistor having a gate to which the received signals are coupled;
- a second transistor having a gate to which a reference signal is coupled;
- and
- a third transistor having a drain that is directly coupled to a drain of the first transistor;
- and
- a series resistor-capacitor (RC) circuit directly coupled to a gate of the third transistor of the comparator circuit to increase bandwidth and reduce interference in the received signals processed by the comparator circuit.
7 more elements
A system, comprising:
- a memory component;
- and
- circuitry included in the memory component to receive signals sent to the memory component, wherein the circuitry comprises:
- a comparator circuit to process the received signals, wherein the comparator circuit includes:
- a first transistor having a gate to which the received signals are coupled;
- a second transistor having a gate to which a reference signal is coupled;
- and
- a third transistor having a drain that is directly coupled to a drain of the first transistor and a fourth transistor having a drain that is directly coupled to a drain of the second transistor;
- a first series resistor-capacitor (RC) circuit directly coupled to a gate of the third transistor of the comparator circuit;
- and
- a second series RC circuit directly coupled to a gate of the fourth transistor of the comparator circuit;
- wherein the first series RC circuit and the second series RC circuit are to increase bandwidth and reduce interference in the received signals processed by the comparator circuit.
9 more elements
A method, comprising:
- receiving, by a memory component of a memory sub-system, signals from a processing device of the memory sub-system;
- processing, by a comparator circuit of the memory component, the received signals, wherein the comparator circuit includes:
- a first transistor having a gate to which the received signals are coupled;
- a second transistor having a gate to which a reference signal is coupled;
- and
- a third transistor having a drain that is directly coupled to a drain of the second transistor;
- reducing, by a series resistor-capacitor (RC) circuit directly coupled to a gate of the third transistor of the comparator circuit, interference in the received signals processed by the comparator circuit;
- and
- increasing, by the series RC circuit directly coupled to the gate of the third transistor of the comparator circuit, bandwidth in the received signals processed by the comparator circuit.
6 more elements
Dependencies are inferred from the claim text.